UPD17708 datasheet(313/356 Pages) NEC

313 / 356 page

313

µPD17704, 17705, 17707, 17708, 17709

21.3 Power-ON Reset

Power-ON reset is effected by raising the supply voltage VDD of the device from a specific level (called a power-

ON clear voltage).

If supply voltage VDD is lower than the power-ON clear voltage, a power-ON clear signal (POC) is output from the

voltage detection circuit shown in Figure 21-1.

When the power-ON clear signal is input to the reset control circuit, the crystal oscillation circuit is stopped and

consequently, the device operation is stopped.

At this time, the program counter, stack, system registers, and control registers are initialized (for the initial value,

refer to the description of each register).

If supply voltage VDD exceeds the power-ON clear voltage, the power-ON clear signal is deasserted, crystal

oscillation is started, and the device waits for release of the halt status by the basic timer 0 carry which has been

initialized to 100 ms. Program execution is started from address 0 at the rising edge of the basic timer 0 carry FF

setting signal 50 ms after the supply voltage has exceeded the power-ON clear voltage.

Normally, the power-ON clear voltage is 3.5 V, but it is 2.2 V in the clock stop status.

The operations of power-ON reset are described in 21.3.1 and 21.3.2.

The operation when supply voltage VDD is raised from 0 V is described in 21.3.3.

Caution Although it is stated that the normal power-ON clear voltage is 3.5 V (MAX.) and that in the clock

stop status is 2.2 V (MAX.), the actual power-ON clear voltage does not exceed these maximum

values.

Figure 21-5. Operation of Power-ON Reset

VDD

Power-ON clear signal

XOUT

BTM0CY flag

setting pulse

5 V

0 V

Power-ON

clear voltage

Power-ON clear released

Oscillation starts

Program starts from

address 0

50 ms

Halt status

Device operation stops

Normal operation

UPD17708 Datasheet(PDF) 313 Page - NEC