UPD17708 datasheet(324/356 Pages) NEC

No. de pieza	UPD17708

Descripción Electrónicos	4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

PDF	356 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NEC [NEC]

Página de inicio	http://www.nec.com/

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324

µPD17704, 17705, 17707, 17708, 17709

21.6.3 Stack pointer overflow/underflow reset

A reset signal is generated if the address or interrupt stack overflows or underflows.

Stack pointer overflow/underflow reset can be used to detect a program hang-up in the same manner as watchdog

timer reset.

The reset signal is generated under the following conditions:

• Interrupt due to overflow or underflow of interrupt stack (4 levels)

• Interrupt due to overflow or underflow of address stack (15 levels)

Reset by stack pointer overflow or underflow initializes all the registers, except the stack overflow selection register,

watchdog timer counter reset register, basic timer 0 carry register, and CE reset timer carry counter.

Generation of stack pointer overflow or underflow reset is detected by the WDTCY flag (R&Reset).

21.6.4 Stack pointer setting flag

The stack overflow/underflow reset selection register can be set only once after power-ON reset on power application

or reset by the RESET pin. This register specifies whether reset by address stack overflow or underflow and reset

by interrupt stack overflow or underflow are enabled or disabled.

UPD17708 Datasheet(PDF) 324 Page - NEC