UPD17708 datasheet(111/356 Pages) NEC

111 / 356 page

111

µPD17704, 17705, 17707, 17708, 17709

11.2.4 When using I/O port as input port

The port pin to be set in the input mode is selected by the I/O selection register corresponding to the port.

Ports P0A, P0B, P0C, P1D, P2A, P2B, P2C, and P2D can be set in the input or output mode in 1-bit units.

P3A, P3B, P3C, and P3D can be set in the input or output mode in 4-bit units.

The pin set in the input mode is floated (Hi-Z) and waits for input of an external signal.

The input data is read by executing a read instruction (such as SKT) to the port register corresponding to

the port pin.

“1” is read from the port register when a high level is input to the corresponding port pin; when a low level

is input to the port pin, “0” is read from the register.

When a write instruction (such as MOV) is executed to the port register corresponding to the pin set in the

input mode, the contents of the output latch are rewritten.

11.2.5 When using I/O port as output port

The port pin to be set in the output mode is selected by the I/O selection register corresponding to the port.

Ports P0A, P0B, P0C, P1D, P2A, P2B, P2C, and P2D can be set in the input or output mode in 1-bit units.

P3A, P3B, P3C, and P3D can be set in the input or output mode in 4-bit units.

The pin set in the output mode outputs the contents of the output latch.

The output data is set by executing a write instruction (such as MOV) to the port register corresponding to

the port pin.

Write “1” to the port register to output a high level to the port pin; write “0” to output a low level. The port pin

can be also floated (Hi-Z) if it is set in the input mode.

If a read instruction (such as SKT) is executed to the port register corresponding to a port pin set in the output

mode, the contents of the output latch are read.

Note, however, that the contents of the output latch of the P0A3 and P0A2 pins may differ from the read

contents because the status of these pins are read as are (refer to 11.2.6).

11.2.6 Cautions on using I/O port (P0A3 and P0A2 pins)

When using the P0A3 and P0A2 pins in the output mode, the contents of the output latch may be rewritten

as shown in the example below.

Example To set the P0A3 and P0A2 pins in the output mode

BANK15

INITFLG P0ABI03, P0ABI02, NOT P0ABI01, NOT P0ABI00 ; Sets P0A3 and P0A2 pins in

output mode

INITFLG P0A3, P0A2, NOT P0A1, NOT P0A0

; Outputs high level to P0A3 and

P0A2 pins

; <1>

CLR1

P0A3

; Outputs low level to P0A3 pin

MACRO EXTEND

AND

.MF.P0A3 SHR 4, #.DF.(NOT P0A3 AND 0FH)

If the P0A2 pin is externally made low when the instruction in the above example <1> is executed,

the contents of the output latch of the P0A2 pin are rewritten to “0” by the CLR1 instruction.

In other words, if an instruction that reads the contents of port register P0A is executed while the

P0A3 or P0A2 pin is set in the output mode, the contents of the output latch are rewritten to the

pin level at that time, regardless of the previous status.

UPD17708 Datasheet(PDF) 111 Page - NEC

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