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UPD17708 Datasheet(PDF) 115 Page - NEC |
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UPD17708 Datasheet(HTML) 115 Page - NEC |
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115 / 356 page ![]() 115 µPD17704, 17705, 17707, 17708, 17709 11.3.4 Status of input port at reset (1) At power-ON reset All the input ports are set in the input mode. All the pull-down resistors of P0D are connected. (2) At WDT&SP reset All the input ports are set in the input mode. All the pull-down resistors of P0D are connected. (3) At CE reset The input ports are set in the input mode. The pull-down resistors of P0D retain the previous status. (4) On execution of clock stop instruction The input ports are set in the input mode. The pull-down resistors of P0D retain the previous status. (5) In halt status The previous status is retained. |
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