UPD17708 datasheet(119/356 Pages) NEC

119 / 356 page

119

µPD17704, 17705, 17707, 17708, 17709

12.2 Interrupt Control Block

An interrupt control block is provided for each peripheral hardware unit. This block detects issuance of an

interrupt request, enables the interrupt, and generates a vector address when the interrupt is accepted.

12.2.1 Configuration and function of interrupt request flag (IRQ

×××)

Each interrupt request flag is set to 1 when an interrupt request is issued by the corresponding peripheral

hardware unit, and is reset to 0 when the interrupt is accepted.

Writing the interrupt request flag to “1” via a window register is equivalent to issuance of the interrupt request.

By detecting the interrupt request flag when an interrupt is not enabled, issuance status of each interrupt

request can be detected.

Once the interrupt request flag has been set, it is not reset until the corresponding interrupt is accepted, or

until “0” is written to the flag via a window register.

Even if two or more interrupt requests are issued at the same time, the interrupt request flag corresponding

to the interrupt that has not been accepted is not reset.

Figures 12-2 through 12-13 show the configuration and function of the respective interrupt request registers.

Figure 12-2. Configuration of Serial Interface 1 Interrupt Request Register

Name

Flag symbol

Address

34H

Read/Write

R/W

Serial interface 1

interrupt request

Power-ON reset

WDT&SP reset

CE reset

Clock stop

Interrupt request not issued

Interrupt request issued

Indicates interrupt request issuance status of serial interface 1

Fixed to “0”

R: Retained

UPD17708 Datasheet(PDF) 119 Page - NEC