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UPD17708 Datasheet(PDF) 166 Page - NEC |
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UPD17708 Datasheet(HTML) 166 Page - NEC |
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166 / 356 page  µPD17704, 17705, 17707, 17708, 17709 166 13.3.3 Count block The count block counts the basic clock with an 8-bit timer 0 counter, reads the count value, and issues an interrupt request if the value of the timer 0 modulo register coincides with its value. Timer 0 counter can be reset by the TM0RES flag. The TM0OVF flag can detect an overflow of the counter. When an overflow occurs, an interrupt request can be issued. The value of the timer 0 counter can be read via data buffer. The value of the timer 0 modulo register can be written or read via data buffer. Figure 13-14 shows the configuration of the timer 0 mode selection register. Figure 13-15 shows the configuration of the timer 0 counter. Figure 13-16 shows the configuration of the timer 0 modulo register. Figure 13-14. Configuration of Timer 0 Mode Selection Register Name Flag symbol b3 T M 0 O V F b2 T M 0 G C E G b1 T M 0 G O E G b0 T M 0 M D Address 2CH Read/Write R/W Timer 0 mode selection Power-ON reset WDT&SP reset CE reset Clock stop 0 1 0 0 0 Modulo counter Gate counter Selects modulo counter or gate counter of timer 0 0 0 0 0 0 0 Rising edge Falling edge Rising edge Falling edge Specifies edge of gate open input signal 0 1 0 0 0 Retained Specifies edge of gate close input signal 0 1 No overflow Overflow Detects timer 0 overflow 0 1 |
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