UPD17708 datasheet(163/356 Pages) NEC

163 / 356 page

163

µPD17704, 17705, 17707, 17708, 17709

13.3 Timer 0

13.3.1 Outline of timer 0

Figure 13-11 shows the outline of timer 0.

The timer 0 is used as timer (modulo mode) by comparing the count value with the previously set value after

the basic clock (100 kHz, 10 kHz, 2 kHz, and 1 kHz) has counted by the 8-bit counter.

The pulse width of the signal input from the TM0G pin can be measured (external gate counter).

Figure 13-11. Outlines Timer 0

Remarks 1. TM0CK1 and TM0CK0 (bits 1 and 0 of timer 0 counter clock selection register: refer to Figure

13-13) set a basic clock frequency.

2. TM0MD (bit 0 of timer 0 mode selection register: refer to Figure 13-14) selects the modulo

counter and gate counter.

3. TM0GOEG (bit 1 of timer 0 mode selection register: refer to Figure 13-14) sets the open edge

of an external gate.

4. TM0GCEG (bit 2 of timer 0 mode selection register: refer to Figure 13-14) sets the close edge

of an external gate.

5. TM0OVF (bit 3 of timer 0 mode selection register: refer to Figure 13-14) detects an overflow

of timer 0 counter.

6. TM0RES (bit 2 of timer 0 counter clock selection register: refer to Figure 13-13) resets timer

0 counter.

Clock selection

4.5 MHz

Gate control

P1A0/TM0G

Start/stop

Timer 0 counter (TM0C)

TM0CK1 flag

TM0CK0 flag

TM0GCEG flag

TM0GOEG flag

TM0MD flag

Coincidence detection circuit

TM0RES

flag

DBF

Gate closed

Overflow

Sets IRQTM0 flag

TM0OVF flag

DBF

Timer 0 modulo register

(TM0M)

UPD17708 Datasheet(PDF) 163 Page - NEC

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