UPD17708 datasheet(196/356 Pages) NEC

196 / 356 page

µPD17704, 17705, 17707, 17708, 17709

196

14.3 Compare Voltage Generation and Compare Blocks

Figure 14-4 shows the configuration of the compare voltage generation block and compare block.

The compare voltage generation block switches a tap decoder according to the 8-bit data set to the A/D

converter reference voltage setting register and generates 256 different of compare voltages V ADCREF.

In other words, this block is an R-string D/A converter.

The supply voltage to this R-string D/A converter is the same as the supply voltage VDD of the device.

The compare block compares voltage VADCIN input from a pin with compare voltage VADCREF.

Comparison can be made in two modes, software mode and hardware mode, which can be selected by the

ADCMD flag.

In the software mode, a compare voltage is set to the A/D converter reference voltage setting register by

software, and one set compare voltage is compared with the input voltage, and the result of the comparison is

detected by the ADCCMP flag.

In the hardware mode, once comparison has been started, the hardware automatically changes the value of

the A/D converter reference voltage setting register. On completion of the comparison, the value of the A/D

converter reference voltage setting register is read and is loaded as an 8-bit data.

Figures 14-5 and 14-6 show the configuration of each flag and A/D converter reference voltage setting

Figure 14-4. Configuration of Compare Voltage Generation and Compare Blocks

DBF

Tap decoder

254

255

VDD

A/D converter reference

voltage setting register (ADCR)

Soft/hard,

start/stop

control block

ADCMD flag

ADCSTT flag

ADCCMP

flag

Comparator

−

2 pF

1/2 VDD

VADCIN

VADCREF

UPD17708 Datasheet(PDF) 196 Page - NEC