UPD17708 datasheet(192/356 Pages) NEC

192 / 356 page

µPD17704, 17705, 17707, 17708, 17709

192

13.6.8 Status at reset

(1) At power-ON reset

The P1B2/PWM2 through P1B0/PWM0 pins are set in the general-purpose output port mode.

The output value is “low level”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

(2) At WDT&SP reset

The P1B2/PWM2 through P1B0/PWM0 pins are set in the general-purpose output port mode.

The output value is “low level”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

(3) On execution of clock stop instruction

The P1B2/PWM2 through P1B0/PWM0 pins are set in the general-purpose output port mode.

The output value is the “previous contents of the output latch”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

(4) At CE reset

The previous status is retained.

That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used,

counting continues.

While timer 3 is being used, the DI status is set (in which all interrupts are disabled).

(5) In halt status

The previous status is retained.

That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used,

counting continues.

UPD17708 Datasheet(PDF) 192 Page - NEC