UPD17708 datasheet(215/356 Pages) NEC

215 / 356 page

215

µPD17704, 17705, 17707, 17708, 17709

15.8 Status at Reset

15.8.1 At power-ON reset

The P1B0/PWM0 through P1B2/PWM2 pins are set in the general-purpose output port mode.

The output value is “low level”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

15.8.2 At WDT&SP reset

The P1B0/PWM0 through P1B2/PWM2 pins are set in the general-purpose output port mode.

The output value is “low level”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

15.8.3 At CE reset

The P1B0/PWM2 through P1B2/PWM2 pins retain the previous status.

That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting

continues.

15.8.4 On execution of clock stop instruction

The P1B0/PWM0 through P1B2/PWM2 pins are set in the general-purpose output port mode.

The output value is the “previous contents of the output latch”.

The value of each PWM data register (including the timer 3 modulo register) is “1FFH”.

15.8.5 In halt status

The P1B0/PWM0 through P1B2/PWM2 pins retain the previous status.

That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting

continues.

UPD17708 Datasheet(PDF) 215 Page - NEC