UPD17708 datasheet(218/356 Pages) NEC

218 / 356 page

218

µPD17704, 17705, 17707, 17708, 17709

Remarks 1.

SIO0CH and SB (bits 3 and 2 of serial I/O0 mode selection register: refer to Figure 16-3) select the

mode of serial I/O0.

SIO0MS (bit 1 of serial I/O0 mode selection register: refer to Figure 16-3) select a master or slave.

SIO0TX (bit 0 of serial I/O0 mode selection register: Figure 16-3) selects reception or transmission.

SIO0CK1 and SIO0CK0 (bits 1 and 0 of serial I/O0 clock selection register: refer to Figure 16-4)

select an internal shift clock frequency.

SIO0WRQ1 and SIO0WRQ0 (bits 1 and 0 of serial I/O0 wait control register: refer to Figure 16-7)

set wait conditions for communication.

SIO0NWT (bit 2 of serial I/O0 wait control register: refer to Figure 16-7) starts communication.

SIO0SF9 and SIO0SF8 (bits 2 and 3 of serial I/O0 status detection register: refer to Figure 16-5)

detect a clock counter.

SBSTT and SBBSY (bits 1 and 0 of serial I/O0 status detection register: refer to Figure 16-5) detect

the start and stop conditions, and clock counter in the I2C bus mode.

SIO0IMD1 and SIO0IMD0 (bits 1 and 0 of serial I/O0 interrupt mode selection register: refer to

Figure 16-9) set interrupt timing.

10.

SBACK (bit 3 of serial I/O0 wait control register: refer to Figure 16-7) reads or sets acknowledge

data.

11.

SIO0WSTT (bit 0 of serial I/O0 wait status judge register: refer to Figure 16-8) detects serial

communication status.

16.2.2 Clock I/O control block and data I/O control block

The clock I/O control block and data I/O control block control the communication mode (I2C bus or serial I/O mode),

the number of pins used (2-wire or 3-wire mode), and transmission or reception operation of serial interface 0.

The 2-wire or 3-wire mode, and I2C bus or serial I/O mode are selected by using the SIO0CH and SB flags.

The SIO0MS flag selects the internal clock (master) or external clock (slave) operation, and the SIO0TX flag selects

reception (RX) or transmission (TX).

Each flag is allocated to the serial I/O0 mode selection register.

Figure 16-3 shows the configuration of the serial I/O0 mode selection register.

Table 16-2 shows the set status of each pin.

As shown in this table, flags that set the input or output mode of each pin must also be manipulated in addition

to the control flags of the serial interface, in order to set each pin.

UPD17708 Datasheet(PDF) 218 Page - NEC