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UPD17708 Datasheet(PDF) 232 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD17708 Datasheet(HTML) 232 Page - NEC

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(7) Shift clock generation timing in I2C bus mode
(a) On releasing wait status from initial status
The initial status is the point where the master operation in the I2C bus mode is selected.
In the wait status, a low level is output to the shift clock pin.
Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (1/5)
Wait period
1/fSC
Shift clock
Wait released
Initialization
1 : 1
(b) During wait operation
<1> Wait status under condition of SIO0WRQ0 and SIO0WRQ1 flags (normal operation)
Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (2/5)
Wait period
Wait released status
1/fSC
Shift clock
Wait under condition of
SIO0WRQ1 and
SIO0WRQ0
Wait released
<2> If forced wait status is set in wait status
Nothing is affected.



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