 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
S25FL256SDPNFAQ Datasheet(PDF) 133 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
S25FL256SDPNFAQ Datasheet(HTML) 133 Page - Cypress Semiconductor |
|
|
133 / 149 page  Document Number: 001-98283 Rev. *M Page 132 of 148 S25FL128S/S25FL256S 51h FFh Read Dual Out latency cycles 52h FFh Read Quad Out mode cycles 53h FFh Read Quad Out latency cycles 54h FFh Dual I/O Read mode cycles 55h FFh Dual I/O Read latency cycles 56h FFh Quad I/O Read mode cycles 57h FFh Quad I/O Read latency cycles Table 67. CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - HPLC DDR Parameter Relative Byte Address Offset Data Description 00h 9Ah Parameter ID (Latency Code Table) 01h 2Ah Parameter Length (The number of following bytes in this parameter. Adding this value to the current location value +1 = the first byte of the next parameter) 02h 05h Number of rows 03h 08h Row length in bytes 04h 46h Start of header (row 1), ASCII “F” for frequency column header 05h 43h ASCII “C” for Code column header 06h 0Dh Read Fast DDR 3-byte address instruction 07h 0Eh Read Fast DDR 4-byte address instruction 08h BDh DDR Dual I/O Read 3-byte address instruction 09h BEh DDR Dual I/O Read 4-byte address instruction 0Ah EDh Read DDR Quad I/O 3-byte address instruction 0Bh EEh Read DDR Quad I/O 4-byte address instruction 0Ch 32h Start of row 2, SCK frequency limit for this row (50 MHz) 0Dh 03h Latency Code for this row (11b) 0Eh 00h Read Fast DDR mode cycles 0Fh 04h Read Fast DDR latency cycles 10h 00h DDR Dual I/O Read mode cycles 11h 04h DDR Dual I/O Read latency cycles 12h 01h Read DDR Quad I/O mode cycles 13h 03h Read DDR Quad I/O latency cycles 14h 42h Start of row 3, SCK frequency limit for this row (66 MHz) 15h 00h Latency Code for this row (00b) 16h 00h Read Fast DDR mode cycles 17h 05h Read Fast DDR latency cycles 18h 00h DDR Dual I/O Read mode cycles 19h 06h DDR Dual I/O Read latency cycles 1Ah 01h Read DDR Quad I/O mode cycles 1Bh 06h Read DDR Quad I/O latency cycles 1Ch 42h Start of row 4, SCK frequency limit for this row (66 MHz) Table 66. CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Continued) Parameter Relative Byte Address Offset Data Description |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Mexican ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
