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S25FL256SDPNFAQ Datasheet(PDF) 136 Page - Cypress Semiconductor

No. de pieza S25FL256SDPNFAQ
Descripción Electrónicos  128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
PDF  149 Pages
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Fabricante Electrónico  CYPRESS [Cypress Semiconductor]
Página de inicio  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S25FL256SDPNFAQ Datasheet(HTML) 136 Page - Cypress Semiconductor

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Document Number: 001-98283 Rev. *M
Page 135 of 148
S25FL128S/S25FL256S
40h
00h
Read Fast mode cycles
41h
08h
Read Fast latency cycles
42h
00h
Read Dual Out mode cycles
43h
08h
Read Dual Out latency cycles
44h
00h
Read Quad Out mode cycles
45h
08h
Read Quad Out latency cycles
46h
04h
Dual I/O Read mode cycles
47h
02h
Dual I/O Read latency cycles
48h
02h
Quad I/O Read mode cycles
49h
05h
Quad I/O Read latency cycles
4Ah
85h
Start of row 6, SCK frequency limit for this row (133 MHz)
4Bh
02h
Latency Code for this row (10b)
4Ch
FFh
Read mode cycles (FFh = command not supported at this frequency)
4Dh
FFh
Read latency cycles
4Eh
00h
Read Fast mode cycles
4Fh
08h
Read Fast latency cycles
50h
FFh
Read Dual Out mode cycles
51h
FFh
Read Dual Out latency cycles
52h
FFh
Read Quad Out mode cycles
53h
FFh
Read Quad Out latency cycles
54h
FFh
Dual I/O Read mode cycles
55h
FFh
Dual I/O Read latency cycles
56h
FFh
Quad I/O Read mode cycles
57h
FFh
Quad I/O Read latency cycles
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR
Parameter Relative
Byte Address Offset
Data
Description
00h
9Ah
Parameter ID (Latency Code Table)
01h
2Ah
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
05h
Number of rows
03h
08h
Row length in bytes
04h
46h
Start of header (row 1), ASCII “F” for frequency column header
05h
43h
ASCII “C” for Code column header
06h
0Dh
Read Fast DDR 3-byte address instruction
07h
0Eh
Read Fast DDR 4-byte address instruction
08h
BDh
DDR Dual I/O Read 3-byte address instruction
09h
BEh
DDR Dual I/O Read 4-byte address instruction
0Ah
EDh
Read DDR Quad I/O 3-byte address instruction
0Bh
EEh
Read DDR Quad I/O 4-byte address instruction
0Ch
32h
Start of row 2, SCK frequency limit for this row (50 MHz)
Table 68. CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Continued)
Parameter Relative
Byte Address Offset
Data
Description



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