UPD17708 datasheet(237/356 Pages) NEC

237 / 356 page

237

µPD17704, 17705, 17707, 17708, 17709

(3) Operation of clock counter

The value of the clock counter is incremented from the initial value “0” each time the rising of the clock pin

has been detected.

The value of the clock counter returns to “0” after it has reached “8”, and the clock counter continues counting.

The clock counter is also reset in the following cases.

•

At reset (power-ON reset, WDT&SP reset, CE reset)

•

On execution of clock stop instruction

•

If data is written to serial I/O0 wait control register

•

If communication mode is changed from 2-wire or 3-wire serial I/O mode to I2C bus mode

(4) Wait operation and Cautions

When the wait status is released, serial data is output (during transmission operation) at the falling of the next

clock, and the wait status is kept released until a condition (wait condition) set by the SIO0WRQ0 and 1 flags

is satisfied.

When the wait condition is satisfied, the shift clock pin is made high, and the operations of the clock counter

and presettable shift register 0 are stopped.

The value of the presettable shift register 0 cannot be read correctly if it is read while the wait status is released

and while the shift clock pin is high.

Correct data cannot be written to the presettable shift register 0 while the wait status is released and while

the shift clock pin is low.

If the forced wait status is specified while the wait status is released, the forced wait status is set as soon as

“0” has been written to the SIO0NWT flag.

The clock output wave is not affected even if the wait status is released again when it has been already released

once. Note, however, that the clock counter is reset.

(5) Interrupt request issuance timing

Interrupt request issuance timing can be selected by the SIO0IMD0 and 1 flags.

For details, refer to 16.2.7 Interrupt control block.

(6) Acknowledge block and its operation

The acknowledge block operates only in the I2C bus mode.

(7) Shift clock generation timing in serial I/O mode

(a) On releasing wait status from initial status

The initial status is the status when the internal clock operation in the serial I/O mode has been selected.

In the wait status, a high level is output to the shift clock pin.

UPD17708 Datasheet(PDF) 237 Page - NEC