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UPD17708 Datasheet(PDF) 241 Page - NEC |
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UPD17708 Datasheet(HTML) 241 Page - NEC |
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241 / 356 page ![]() 241 µPD17704, 17705, 17707, 17708, 17709 16.2.11 Operation of serial interface 0 Tables 16-4 through 16-6 outlines the operations in each communication mode. Table 16-4. Outline of Operation in I2C Bus Mode Operation Mode I2C Bus Mode Slave operation (SIO0MS = 0) Master operation (SIO0MS = 1) Reception Transmission Reception Transmission Item (SIO0TX = 0) (SIO0TX = 1) (SIO0TX = 0) (SIO0TX = 1) Status of SDA/P0A3 When P0ABIO3 = 0 Outputs contents of When P0ABIO3 = 0 Outputs contents of each pin Floating SIO0SFR at falling of Floating SIO0SFR at falling of Waits for input of external clock Waits for input of internal clock external data regardless of external data regardless of P0ABIO3 When P0ABIO3 = 1 P0ABIO3 When P0ABIO3 = 1 General-purpose General-purpose output port output port Outputs content of Outputs content of output latch output latch SCL/P0A2 When P0ABIO2 = 0 Outputs internal clock regardless of P0ABIO2 Floating Waits for input of external data When P0ABIO2 = 1 General-purpose output port Outputs content of output latch Clock counter Incremented at rising of SCL pin Operation of Output Not output Shifted from MSB Not output Shifted from MSB presettable each time SCL falls each time SCL falls shift register 0 and is output and is output Input Shifted from LSB each time SCL rise and is input Wait operation In wait SCL and SDA pins SCL pin is floated SCL pin outputs low SCL pin outputs low status are floated and SDA pin retains level and SDA pin is level and SDA pin its status floated retains its status Wait SCL pin is floated SCL pin is floated SCL pin outputs SCL pin outputs released and waits for input of and waits for input of internal clock. internal clock. external clock. external clock. SDA pin is floated SDA pin outputs data SDA pin is floated and SDA pin outputs data and waits for external each time SCL pin falls waits for external data each time SCL pin falls data Acknowledge ACK output at falling ACK input at rising ACK output at falling ACK input at rising of 8th clock of 9th clock of 8th clock of 9th clock ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– |
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