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UPD17708 Datasheet(PDF) 248 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD17708 Datasheet(HTML) 248 Page - NEC

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16.3.4 Presettable shift register 1
Presettable shift register 1 is an 8-bit shift register that writes serial out data and reads serial in data.
This register writes or reads data via data buffer.
It outputs the contents of the most significant bit (MSB) from the serial data I/O pin in synchronization with the falling
edge of the shift clock (during transmission operation), and reads data to the least significant bit (LSB) in synchronization
with the rising edge of the serial clock.
Figure 16-18 shows the configuration of the presettable shift register 1.
Figure 16-18. Configuration of Presettable Shift Register 1
Note
Data may be destroyed if the PUT or GET instruction is executed during serial communication. For details,
refer to 16.3.7 Cautions on setting and reading data.
16.3.5 Wait control block
The wait control block keeps communication waiting or releases communication from the wait status.
Serial communication is started when communication is released from the wait status by using the SIO1TS flag
of the serial I/O1 mode selection register.
Communication is set in the wait status eight clocks after the wait status has been released and communication
has been started.
The communication status can be detected by using the SIO1TS flag. To do so, detect the status of the SIO1TS
flag after setting this flag to “1”.
If “0” is written to the SIO1TS flag when communication is released from the wait status, the wait status is set. This
wait status is called forced wait status.
For the configuration of the serial I/O1 mode selection register, refer to Figure 16-17.
Data buffer
DBF3
Don't care
DBF2
Don't care
Name
Presettable
shift register 1
Symbol
SIO1SFR
Peripheral
register
04H
DBF1
DBF0
b3 b2
b1 b0
L
S
B
b7
M
S
B
b6
b5 b4
Peripheral register
D3 D2 D1 D0
D7 D6 D5 D4
D7
← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0
Serial out
Serial in
Transfer data
Valid data
Sets serial out data and reads serial in data
GETNote
PUTNote
8



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