UPD17708 datasheet(244/356 Pages) NEC

No. de pieza	UPD17708

Descripción Electrónicos	4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

PDF	356 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NEC [NEC]

Página de inicio	http://www.nec.com/

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244

µPD17704, 17705, 17707, 17708, 17709

16.2.12 Status of serial interface 0 at reset

(1) At power-ON reset

Each pin is set in the general-purpose input port mode.

The contents of presettable shift register 0 are undefined.

(2) At WDT&SP reset

Each pin is set in the general-purpose input port mode.

The contents of presettable shift register 0 are undefined.

(3) On execution of clock stop instruction

Each pin is set in the general-purpose I/O port mode and remains in the previous input or output mode.

The contents of presettable shift register 0 are undefined.

(4) At CE reset

Each pin is set in the general-purpose I/O port mode and remains in the previous input or output mode.

The contents of presettable shift register 0 are undefined.

(5) In halt status

Each pin retains its set status.

Output of the internal clock is stopped in the status where the HALT instruction is executed.

When an external clock is used, the operation continues even if the HALT instruction is executed.

Presettable shift register 0 retains the previous value.

UPD17708 Datasheet(PDF) 244 Page - NEC