UPD17708 datasheet(259/356 Pages) NEC

No. de pieza	UPD17708

Descripción Electrónicos	4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

PDF	356 Pages

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Fabricante Electrónico	NEC [NEC]

Página de inicio	http://www.nec.com/

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259 / 356 page

259

µPD17704, 17705, 17707, 17708, 17709

Figure 17-4. Setting Division Value (N Value) of PLL Frequency Synthesizer

Note

The value of PLLSCNF flag is transferred when a write (PUT) instruction is executed to the PLL data register

(PLLR). Therefore, data must be set to the PLLSCNF flag before executing the write instruction to the PLL

data register.

Data buffer

DBF3

DBF2

Name

PLL data

Symbol

PLLR

Peripheral

address

42H

DBF1

DBF0

b3 b2 b1 b0

b10

b11

b12

b13

b14

b15

b16

b6 b5 b4

b10 b9 b8 b7

b13 b12

b15 b14

b11

Peripheral register

PLL

N value data

(17 bits)

Direct division

mode

don't care

Setting prohibited

Division value N: N = x

Setting prohibited

Division value N: N = x

don't care

15 (00FH)

212–1 (FFFH)

Pulse swallow

mode

Transfer data

Valid data

Sets high-order 16 bits of division value

Sets least significant bit of division value Note

Name

PLL mode

selection

address

10H

b2 b1 b0

GET

PUT

Sets division value (N value) of PLL

frequency synthesizer

1023 (3FFH)

217–1 (1FFFFH)

don't care

16 (010H)

1024 (400H)

UPD17708 Datasheet(PDF) 259 Page - NEC

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