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UPD17708 Datasheet(PDF) 261 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
Logo NEC - NEC

UPD17708 Datasheet(HTML) 261 Page - NEC

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µPD17704, 17705, 17707, 17708, 17709
Figure 17-6. Configuration of PLL Reference Frequency Selection Register
Remark
When the PLL frequency synthesizer is disabled by the PLL reference frequency selection register, the
VCOH and VCOL pins are internally pulled down. The EO1 and EO0 pins are floated.
Name
Flag symbol
b3
P
L
L
R
F
C
K
3
b2
P
L
L
R
F
C
K
2
b1
P
L
L
R
F
C
K
1
b0
P
L
L
R
F
C
K
0
Address
11H
Read/Write
R/W
PLL reference
frequency selection
Power-ON reset
WDT&SP reset
CE reset
Clock stop
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1.25 kHz
2.5 kHz
5 kHz
10 kHz
6.25 kHz
12.5 kHz
25 kHz
50 kHz
3 kHz
9 kHz
18 kHz
Setting prohibited
1 kHz
20 kHz
Setting prohibited
PLL disable
Sets reference frequency fr of PLL frequency synthesizer
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1



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