UPD17708 datasheet(271/356 Pages) NEC

No. de pieza	UPD17708

Descripción Electrónicos	4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

PDF	356 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NEC [NEC]

Página de inicio	http://www.nec.com/

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271 / 356 page

271

µPD17704, 17705, 17707, 17708, 17709

Note that data must be set to the PLLSCNF flag before a write (PUT) instruction is executed to the PLL data

Example

SET1

PLLSCNF

MOV

DBF0, #0

MOV

DBF1, #4

MOV

DBF2, #4

PUT

PLLR, DBF

17.7 Status at Reset

17.7.1 At power-ON reset

The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized

to 1111B.

17.7.2 At WDT&SP reset

The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized

to 1111B.

17.7.3 On execution of clock stop instruction

The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized

to 1111B.

17.7.4 At CE reset

The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized

to 1111B.

17.7.5 In halt status

The set status is retained if the CE pin is high.

UPD17708 Datasheet(PDF) 271 Page - NEC