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UPD17708 Datasheet(PDF) 272 Page - NEC |
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UPD17708 Datasheet(HTML) 272 Page - NEC |
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272 / 356 page ![]() 272 µPD17704, 17705, 17707, 17708, 17709 18. FREQUENCY COUNTER 18.1 Outline of Frequency Counter Figure 18-1 outlines the frequency counter. The frequency counter has an IF counter function to count the intermediate frequency (IF) of an external input signal and an external gate counter (FCG: Frequency Counter for external Gate signal) to detect the pulse width of an external input signal. The IF counter function counts the frequency input to the P1C0/FMIFC or P1C1/AMIFC pin at fixed intervals (1 ms, 4 ms, 8 ms, or open) by using a 16-bit counter. The external gate counter function counts the frequency of the internal clock (1 kHz, 100 kHz, 900 kHz) from the rising to the falling of the signal input to the P2A1/FCG1 or P2A0/FCG0 pin. The IF counter and external gate counter functions cannot be used at the same time. Figure 18-1. Outline of Frequency Counter I/O selection block Gate time control block Start/stop control block IF counter (16 bits) P2A1/FCG1 FCGCH1 flag FCGCH0 flag IFCCK1 flag IFCCK0 falg IFCSTRT flag DBF IFCGOSTT flag IFCRES flag IFCMD1 flag IFCMD0 flag P2A0/FCG0 P1C0/FMIFC P1C1/AMIFC Remarks 1. FCGCH1 and FCGCH0 (bits 1 and 0 of FCG channel selection register: refer to Figure 18-4) select the pin used for the external gate counter function. 2. IFCMD1 and IFCMD0 (bits 3 and 2 of IF counter mode selection register: refer to Figure 18-3) select the IF counter or external gate counter function. 3. IFCCK1 and IFCCK0 (bits 1 and 0 of IF counter mode selection register: refer to Figure 18-3) select the gate time of the IF counter function and the reference frequency of the external gate counter function. 4. IFCSTRT (bit 1 of IF counter control register: refer to Figure 18-6) control starting of the IF counter and external gate counter functions. 5. IFCGOSTT (bit 0 of IF counter gate status detection register: refer to Figure 18-7) detects opening/ closing the gate of the IF counter function. 6. IFCRES (bit 0 of IF counter control register: refer to Figure 18-6) reset the count value of the IF counter. |
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