UPD17708 datasheet(293/356 Pages) NEC

293 / 356 page

293

µPD17704, 17705, 17707, 17708, 17709

20.2 Halt Function

20.2.1 Outline of halt function

The halt function stops the operating clock of the CPU by executing the “HALT h” instruction.

When this instruction is executed, the program is stopped until the halt status is later released. Therefore, the

current consumption of the device in the halt status is reduced by the operating current of the CPU.

The halt status is released by using basic timer 0 carry FF, interrupt, or port input (P0D).

The release condition is specified by operand “h” of the “HALT h” instruction.

20.2.2 Halt status

In the halt status, all the operations of the CPU are stopped. In other words, execution of the program is stopped

at the “HALT h” instruction. However, the peripheral hardware units continue the operation specified before execution

of the “HALT h” instruction.

For the operation of each peripheral hardware unit, refer to 20.4 Device Operation in Halt and Clock Stop Status.

20.2.3 Halt release condition

Figure 20-2 shows the halt release condition.

The halt release condition is specified by 4-bit data specified by operand “h” of the “HALT h” instruction.

The halt status is released when the condition specified by “1” in operand “h”.

When the halt status is released, program execution is started from the instruction after the “HALT h” instruction.

If the halt status is released by an interrupt, the operation to be performed after the halt status has been released

differs depending on whether the interrupts are enabled (EI status) or disabled (DI status) when an interrupt source

(IRQxxx = 1) is issued with the interrupt (IPxxx = 1) enabled.

If two or more releasing conditions are specified, the halt status is released when one of the specified condition

is satisfied.

If 0000B is set as halt release condition “h”, no releasing condition is set. If the device is reset (by means of power-

ON reset, WDT&SP reset, or CE reset) at this time, the halt status is released.

Figure 20-2. Halt Release Condition

Operand

HALT h (4 bits)

b3 b2

b1 b0

Released when high level is input to port 0D

Released when basic timer 0 carry FF is set to 1

Undefined (Fix this bit to “0”.)

Released when interrupt is accepted

Not released even if condition is satisfied

Released if condition is satisfied

Sets halt status releasing condition

UPD17708 Datasheet(PDF) 293 Page - NEC