UPD17708 datasheet(294/356 Pages) NEC

294 / 356 page

294

µPD17704, 17705, 17707, 17708, 17709

20.2.4 Releasing halt by input port (P0D)

The halt releasing condition using an input port is specified by the “HALT 0001B” instruction.

When the halt releasing condition using an input port is specified, the halt status is released if a high level is input

to one of the P0D0 through P0D3 pins.

The P0D0 through P0D3 pins are multiplexed with the A/D converter input pins AD0 through AD3, and the halt status

is not released when these pins are used as A/D converter input pins.

An example is given below.

•

To use as key matrix

The P0D0 through P0D3 pins are general-purpose input port pins which can be set in the input or output mode

in 1-bit units and can be connected to an internal pull-down resistor. If connection of the internal pull-down

resistor is specified by software, an external resistor can be eliminated as shown in this example (the internal-

pull down resistor is connected at power-ON reset).

The “HALT 0001B” instruction is executed after the general-purpose output ports for key source signal are made

high. Note that if an alternate switch is used as shown by switch A in the above figure, the halt status is released

immediately because a high level is input to the P0D0/AD0 pin while switch A is closed.

P0D3/AD3

P0DPLD3 flag

P0D2/AD2

P0D1/AD1

P0D0/AD0

Switch A

General-purpose output port

Latch

UPD17708 Datasheet(PDF) 294 Page - NEC