UPD17708 datasheet(296/356 Pages) NEC

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296

µPD17704, 17705, 17707, 17708, 17709

Example Releasing halt status by timer 0 and INT0 pin interrupts

In this example, the halt status is released and processing B is executed when timer 0 interrupt is

accepted. And processing A is executed when INT0 pin interrupt is accepted.

Each time the halt status has been released, processing C is executed.

HLTINT

DAT

1000B

; Symbol definition

START:

; Address 0000H

MAIN

;*** Interrupt vector address ***

NOP

; SI01

NOP

; SI00

NOP

; TIMER3

NOP

; TIMER2

NOP

; TIMER1

INTTM0

; Branches to timer 0 interrupt processing

NOP

; INT4

NOP

; INT3

NOP

; INT2

NOP

; INT1

INT0

; Branches to INT0 interrupt processing

NOP

; CE DOWN EDGE

INT0:

; INT0 pin interrupt vector address (000BH)

Processing A

; INT0 pin interrupt processing

RETI

INTMM0:

Processing B

; Timer 0 interrupt processing

RETI

MAIN:

INITFLG

NOT TMOCK1, TM0CK0

; Sets timer 0 count clock to 100

µs

MOV

DBF1, #0

MOV

DBF0, #0AH

PUT

TM0M,DBF

; Sets time interval of timer 0 interrupt to 1 ms

SET2

TM0RES, TM0EN

; Resets and starts timer 0

SET2

IPTM0, IP0

; Enables INT0 and timer 0 interrupts

LOOP:

Processing C

; Main routine processing

; Enables all interrupts

HALT

HLTINT

; Specifies releasing halt status by interrupt

;<1>

LOOP

If the INT0 pin interrupt request and timer 0 interrupt request are issued simultaneously in the halt status,

processing A for the INT0 pin, which has the higher hardware priority, is executed.

After execution of processing A and when “RETI” is executed, the program branches to the “BR LOOP”

instruction of <1>. However, the “BR LOOP” instruction is not executed, and timer 0 interrupt is immediately

accepted.

When the “RETI” instruction is executed after processing B of timer 0 interrupt has been executed, the

“BR LOOP” instruction is executed.

UPD17708 Datasheet(PDF) 296 Page - NEC

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