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UPD17708 Datasheet(PDF) 158 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD17708 Datasheet(HTML) 158 Page - NEC

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Example Example of timer updating processing and BTM0CY flag detection time interval
START:
CLR2
BTM0CK1, BTM0CK0
; Sets BTM0CY flag setting pulse to 10 Hz (100 ms)
BTIMER:
; <1>
SKT1
BTM0CY
; Updates timer if BTM0CY flag is “1”
BR
AAA
Timer updating
BR
BTIMER
AAA:
Processing A
BR
BTIMER
The timing chart of the above program is shown below.
(3) Compensating basic timer 0 carry at CE reset
Next, an example of compensating the timer at CE reset is described below.
As shown in the example below, the timer must be compensated at CE reset “if the BTM0CY flag is used
for power failure detection and if the BTM0CY flag is used for a watch timer”.
The BTM0CY flag is reset (to 0) first on power application (power-ON reset), and is disabled from being
set until it is read once by the “PEEK” instruction.
If the CE pin goes high, CE reset is effected in synchronization with the rising edge of the BTM0CY flag
setting pulse. At this time, the BTM0CY flag is set (to 1) and the timer is started.
By detecting the status of the BTM0CY flag at system reset (power-ON reset or CE reset), therefore, it
can be identified whether a power-ON reset or CE reset has been effected (power failure detection). That
is, power-ON reset has been effected if the flag is “0”, and CE reset has been effected if it is “1”.
At this time, the watch timer must continue operating even if CE reset has been effected.
However, because the BTM0CY flag is reset to 0 when it is read to detect a power failure, the set status
(1) of the BTM0CY flag is overlooked once. If the delay function of CE reset is used, the value set to
the CE reset timer carry counter (control register address 06H) is overlooked.
Consequently, the watch timer must be updated if CE reset is identified by means of power failure
detection.
For the details of power failure detection, refer to 21. RESET.
tSET
H
CE pin
BTM0CY detection interval
tCHECK
Timer updating processing
tTIMER
BTM0CY flag
BTM0CY flag
setting pulse
L
H
L
1
<1> SKT1
BTM0CY
<2> SKT1
BTM0CY
CE reset
0
If this timer updating processing
time is too long, CE reset is effected
during processing.



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