UPD17708 datasheet(161/356 Pages) NEC

161 / 356 page

161

µPD17704, 17705, 17707, 17708, 17709

(4) If BTM0CY flag is detected at the same time as CE reset

As described in (3) above, CE reset is effected as soon as the BTM0CY flag is set to 1.

If the instruction that reads the BTM0CY flag happens to be executed at the same time as CE reset at

this time, the BTM0CY flag reading instruction takes precedence.

Therefore, if the next setting the BTM0CY flag (rising of BTM0CY flag setting pulse) after the CE pin has

gone high coincides with execution of the BTM0CY flag reading instruction, CE reset is effected at “the

next timing at which the BTM0CY flag is set”.

This operation is illustrated in Figure 13-10.

Figure 13-10. Operation When CE Reset Coincides with BTM0CY Flag Reading Instruction

Consequently, if the BTM0CY flag detection time interval coincides with the BTM0CY flag setting time

in a program that cyclically detects the BTM0CY flag, CE reset is never effected.

Therefore, the following point must be noted.

Because one instruction cycle is 1.78

µs (1/562.5 kHz), a program that detects the BTM0CY flag once,

say, every 1125 instructions, reads the BTM0CY flag every 1.78

µs × 1125 = 2 ms.

Because the timer time setting pulse is 100 ms at this time, if setting and detection of the BTM0CY flag

coincide once, CE reset is never effected.

BTM0CY flag

setting pulse

BTM0CY flag

CE pin

1.78 s

SKT1 BTM0CY

(PEEK ···)

SKT1

BTM0CY

CE reset

(SKT ···)

BTM0CY flag

setting pulse

BTM0CY flag

Instruction

Embedded macro

PEEK WR, . MF. BTM0CY SHR 4

SKT

WR, #. DF. BTM0CY AND 000FH

If BTM0CY flag is read at this time, CE reset is

effected delayed once.

Originally, program is started from address 0000H here.

However, CE reset is not effected because it happens to

coincide with program that reads BTM0CY flag.

SKT1

BTM0CY

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