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UPD17708 Datasheet(PDF) 189 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
Logo NEC - NEC

UPD17708 Datasheet(HTML) 189 Page - NEC

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µPD17704, 17705, 17707, 17708, 17709
13.6.4 Count block
The count block counts the basic clock with timer 3 and issues an interrupt request when the count value of
timer 3 coincides with the value of the timer 3 modulo register.
Timer 3 counter can be reset by the TM3RES flag.
Because the PWM data register 2 (PWMR2) and timer 3 modulo register (TM3M) are multiplexed, these
registers cannot be used at the same time.
When timer 3 is used, the PWM data register 1 (PWMR1) and PWM data register 0 (PWMR0) can be used
as 9-bit data latches (refer to 15. D/A CONVERTER (PWM mode)).
Figure 13-28. Configuration of Timer 3 Modulo Register
Note
This register is multiplexed with the PWM data register.
Sets modulo data of timer 3
Data buffer
DBF3
DBF2
Name
Symbol
Address
Bit
Data
DBF1
DBF0
b3 b2
b1 b0
b7
b8
b9
0
b10
0
b11
0
b12
0
b13
0
b14
0
b15
0
b6
b5 b4
Timer 3 modulo registerNote
TM3M
46H
Power-ON reset
WDT&SP reset
CE reset
Clock stop
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Retained
Transfer data
Valid data
0
x
Modulo counter value
Fixed to “0”
1FFH
16 bits
GET
PUT



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