S25FL256SDPNFAQ datasheet(101/149 Pages) CYPRESS

101 / 149 page

Document Number: 001-98283 Rev. *M

Page 100 of 148

S25FL128S/S25FL256S

Figure 9.33 Continuous DDR Quad I/O Read Subsequent Access (4-byte Address, EHPLC=01b)

Note:

1. Example DLP of 34h (or 00110100).

9.5

Program Flash Array Commands

9.5.1

Program Granularity

9.5.1.1 Automatic ECC

Each 16 byte aligned and 16 byte length Programming Block has an automatic Error Correction Code (ECC) value. The data block

plus ECC form an ECC unit. In combination with Error Detection and Correction (EDC) logic the ECC is used to detect and correct

any single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set for the entire

ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable the Error Detection and

Correction (EDC) function. A sector erase is needed to again enable Automatic ECC on that Programming Block. The 16 byte

Program Block is the smallest program granularity on which Automatic ECC is enabled.

These are automatic operations transparent to the user. The transparency of the Automatic ECC feature enhances data accuracy

for typical programming operations which write data once to each ECC unit but, facilitates software compatibility to previous

generations of FL-S family of products by allowing for single byte programming and bit walking in which the same ECC unit is

programmed more than once. When an ECC unit has Automatic ECC disabled, EDC is not done on data read from the ECC unit

location.

An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have been detected

and corrected in the ECC unit data or the ECC (See Section 7.5.6 ECC Status Register (ECCSR) on page 54.) The ECC Status

EDC is applied to all parts of the Flash address spaces other than registers. An ECC is calculated for each group of bytes protected

and the ECC is stored in a hidden area related to the group of bytes. The group of protected bytes and the related ECC are together

called an ECC unit.

ECC is calculated for each 16 byte aligned and length ECC unit.



Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag.



Sector erase resets all ECC bits and ECC disable flags in a sector to the default state (enabled).



ECC is programmed as part of the standard Program commands operation.



ECC is disabled automatically if multiple programming operations are done on the same ECC unit.



Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16-byte ECC unit.



The ECC disable flag is programmed when ECC is disabled.



To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased.



To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored for that

unit and not disabled.



The calculation, programming, and disabling of ECC is done automatically as part of a programming operation. The detection and

correction, if needed, is done automatically as part of read operations. The host system sees only corrected data from a read

operation.



ECC protects the OTP region - however a second program operation on the same ECC unit will disable ECC permanently on that

ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is prohibited).

0123

456

32 Bit Address

Mode

High-Z Bus Turn-around

Optional Data Learning Pattern

Data 0

Data 1

4 cycles

1 cycle

7 cycle Dummy

1 cycle per data

CS#

SCK

IO0

IO1

IO2

IO3

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