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S25FL256SDPNFAQ Datasheet(PDF) 104 Page - Cypress Semiconductor |
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S25FL256SDPNFAQ Datasheet(HTML) 104 Page - Cypress Semiconductor |
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104 / 149 page ![]() Document Number: 001-98283 Rev. *M Page 103 of 148 S25FL128S/S25FL256S 9.5.3 Quad Page Program (QPP 32h or 38h, or 4QPP 34h) The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). The Quad-input Page Program (QPP) command allows up to a page size (either 256 or 512 bytes) of data to be loaded into the Page Buffer using four signals: IO0-IO3. QPP can improve performance for PROM Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4 bits of data per clock cycle. Systems with faster clock speeds do not realize as much benefit for the QPP command since the inherent page program time becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP command is 80 MHz. To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A Write Enable command must be executed before the device will accept the QPP command (Status Register 1, WEL=1). The instruction 32h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 32h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 38h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 38h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 34h is followed by a 4-byte address (A31-A0) and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory locations. The programming page is aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16 byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled. All other functions of QPP are identical to Page Program. The QPP command sequence is shown in Figure 66. Figure 66. Quad 512-Byte Page Program Command Sequence (3-Byte Address, 32h or 38h) 1 3 2 10 9 8 7 6 5 4 0 31 30 29 28 Instruction 24-Bit Address 23 21 22 1 3 2 0 36 35 34 33 32 39 38 37 2 0 1 3 4 5 6 7 Byte 1 44 43 42 41 40 47 46 45 52 51 50 49 48 55 54 53 SCK IO0 SCK IO0 * * 2 0 1 3 4 5 6 7 * Byte 2 5 6 2 0 1 3 4 6 7 Byte 3 * 2 0 1 3 4 5 6 7 * Byte 4 IO1 IO2 IO3 6 2 0 1 3 4 5 7 Byte 5 * * Byte 6 Byte 7 * * Byte 8 Byte 9 * * Byte 10 Byte 11 * * Byte 12 Byte 509 * * Byte 510Byte 511 * * Byte 512 IO1 IO2 IO3 CS# CS# 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 6 2 0 1 3 4 5 7 *MSB |
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