S25FL256SDPNFAQ datasheet(102/149 Pages) CYPRESS

102 / 149 page

Document Number: 001-98283 Rev. *M

Page 101 of 148

S25FL128S/S25FL256S

9.5.1.2 Page Programming

Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move

data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single

programming command. Page Programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation.

The page size is determined by the Ordering Part Number (OPN). The page is aligned on the page size address boundary. It is

possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16

byte length and aligned Program Blocks be written. For the very best performance, programming should be done in full pages of 512

bytes aligned on 512-byte boundaries with each Page being programmed only once.

9.5.1.3 Single Byte Programming

Single Byte Programming allows full backward compatibility to the standard SPI Page Programming (PP) command by allowing a

single byte to be programmed anywhere in the memory array. While single byte programming is supported, this will disable

Automatic ECC on the 16 byte ECC unit where the byte is located

9.5.2

Page Program (PP 02h or 4PP 12h)

The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page

Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the

device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in

the Status Register to enable any write operations.

The instruction



02h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or



02h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or



12h is followed by a 4-byte address (A31-A0)

and at least one data byte on SI. Depending on the device OPN, the page size can either be 256 or 512 bytes. Up to a page can be

provided on SI after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been provided. If the 9 least

significant address bits (A8-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed

from the start address of the same page (from the address whose 9 least significant bits (A8-A0) are all zero) i.e. the address wraps

within the page aligned address boundaries. This is a result of only requiring the user to enter one single page address to cover the

entire page boundary.

If less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the provided address

within the page, without having any affect on the other bytes of the same page.

For optimized timings, using the Page Program (PP) command to load the entire page size program buffer within the page boundary

will save overall programming time versus loading less than a page size into the program buffer.

The programming process is managed by the flash memory device internal control logic. After a programming command is issued,

the programming operation status can be checked using the Read Status Register-1 command. The WIP bit (SR1[0]) will indicate

when the programming operation is completed. The P_ERR bit (SR1[6]) will indicate if an error occurs in the programming operation

that prevents successful completion of programming.

S25FL256SDPNFAQ Datasheet(PDF) 102 Page - Cypress Semiconductor

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