S25FL256SDPNFAQ datasheet(116/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

9.8.6

PPB Program (PPBP E3h)

Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After

the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to

enable any write operations.

The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 32-bit address

selecting location zero within the desired sector (note, the high order address bits not used by a particular density device must be

zero).

The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other

programming operation.

CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is initiated. While the PPBP operation is in

progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a

1 during the self-timed PPBP operation, and is a 0 when it is completed. When the PPBP operation is completed, the Write Enable

Latch (WEL) is set to a 0.

Figure 81. PPBP Command Sequence

9.8.7

PPB Erase (PPBE E4h)

The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the device, a Write

Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status

The instruction E4h is shifted into SI by the rising edges of the SCK signal.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the

beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CS#

being driven to the logic high state after the eighth bit of the instruction, the PPB erase operation will not be executed.

With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has

been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.

Erase suspend is not allowed during PPB Erase.

Figure 82. PPB Erase Command Sequence

IInstruction

32 bit Address

SCK

MSB

High Impedance

MSB

Instruction

SCK

High Impedance

CS#

MSB

S25FL256SDPNFAQ Datasheet(PDF) 116 Page - Cypress Semiconductor

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