S25FL256SDPNFAQ datasheet(119/149 Pages) CYPRESS

119 / 149 page

Document Number: 001-98283 Rev. *M

Page 118 of 148

S25FL128S/S25FL256S

Figure 9.41 Password Unlock Command Sequence

9.9

Reset Commands

9.9.1

Software Reset Command (RESET F0h)

The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile FREEZE bit in the

Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The Freeze bit and the PPB Lock bit will

remain set at their last value prior to the software reset. To clear the FREEZE bit and set the PPB Lock bit to its protection mode

selected power on state, a full power-on-reset sequence or hardware reset must be done. Note that the non-volatile bits in the

configuration register, TBPROT, TBPARM, and BPNV, retain their previous state after a Software Reset. The Block Protection bits

BP2, BP1, and BP0, in the status register will only be reset if they are configured as volatile via the BPNV bit in the Configuration

Register (CR1[3]) and FREEZE is cleared to zero . The software reset cannot be used to circumvent the FREEZE or PPB Lock bit

protection mechanisms for the other security configuration bits. The reset command is executed when CS# is brought to high state

and requires tRPH time to execute.

Figure 85. Software Reset Command Sequence

Instruction

Password

210

SCK

MSB

High Impedance

CS#

MSB

Instruction

SCK

CS#

S25FL256SDPNFAQ Datasheet(PDF) 119 Page - Cypress Semiconductor