S25FL256SDPNFAQ datasheet(118/149 Pages) CYPRESS

118 / 149 page

Document Number: 001-98283 Rev. *M

Page 117 of 148

S25FL128S/S25FL256S

9.8.11 Password Program (PASSP E8h)

Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be

issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable

Latch (WEL) to enable the PASSP operation.

The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit

to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP command is ignored.

The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on

SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.

CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation

is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit

is a 1 during the self-timed PASSP cycle, and is a 0 when it is completed. The PASSP command can report a program error in the

P_ERR bit of the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The

maximum clock frequency for the PASSP command is 133 MHz.

Figure 9.40 Password Program Command Sequence

9.8.12 Password Unlock (PASSU E9h)

The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on

SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.

CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSU command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PASSU operation is initiated. While the PASSU operation

is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit

is a 1 during the self-timed PASSU cycle, and is a 0 when it is completed.

If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by

setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary to use the CLSR command to

clear the status register, the RESET command to software reset the device, or drive the RESET# input low to initiate a hardware

reset, in order to return the P_ERR and WIP bits to 0. This returns the device to standby state, ready for new commands such as a

retry of the PASSU command.

If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU command is 133 MHz.

Instruction

Password

210

SCK

MSB

High Impedance

CS#

MSB

S25FL256SDPNFAQ Datasheet(PDF) 118 Page - Cypress Semiconductor