STLC5466 datasheet(62/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.35 - Time Slot Assigner Address Register 2

TAAR2 (54)H

This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the

switching matrix.

• N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working.

The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.

VI.36 - Time Slot Assigner Data Register 2

TADR2 (56)H

This register concerns the second 32 HDLC controller named HDLC2 connected to input6/output6 of the

switching matrix

A16/23: These 8 bits define two areas of the shared Memory; each area is multiple of 64Kbytes. The

shared Memory is split in two parts:

the upper part of the shared Memory is affected to the first half part of the Fetch Memory located

in the microprocessor interface,

the lower part is affected to the second half part of the Fetch Memory.

Particular case: A16/23=0. One area of the shared Memory is defined, the two parts of the Fetch

Memory are merged.

bit15

bit8

bit7

bit0

TS4

TS3

TS2

TS1

TS0

READ

HDI

After reset (0100)H

READ

: READ MEMORY

READ = 1, Read Time slot Assigner Memory 2.

READ = 0, Write Time slot Assigner Memory 2.

TS0/4

: TIME SLOTS0/4

These five bits define one of 32 time slots in which a channel is set-up or not.

HDI

: HDLC2 INIT

HDI = 1, TSA2 Memory, Tx HDLC2, Tx DMA2, Rx HDLC2, Rx DMA2 are reset. An automate

writes data from Time slot Assigner Data Register 2 (TADR2) (except CH0/4 bits) into each

TSA Memory location. If the microprocessor reads Time slot Assigner Memory 2 after HDLC2

INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot

Assigner Address Register 2.

HDI = 0, Normal state.

bit15

bit8

bit7

bit0

V11

V10

CH4

CH3

CH2

CH1

CH0

After reset (0000)H

CH0/4

: CHANNEL0/4

These five bits define one of 32 channels associated to time slot defined by the previous Reg-

ister 2(TAAR2).

V1/8

: VALIDATION

The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at

1 respectively.

V1 to V8 are at “0’: the subchannels are ignored.

V1 corresponds to the first bit received during the current time slot.

V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission

the first bit transmitted is taken into account.

V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received

and in transmission the last bit transmitted in transmission.

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