STLC5466 datasheet(63/130 Pages) STMICROELECTRONICS

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STLC5466

VI.37 - HDLC Transmit Command Register 2

HTCR2 (58)H

: VALIDATION SUBCHANNEL

V 9 = 1, each V1/8 bit is taken into account once every 250

µs.

In transmit direction, data is transmitted consecutively during the time slot of the current frame

and during the same time slot of the next frame.Id est.: the same data is transmitted in two con-

secutive frames.

In receive direction, HDLC controller fetches data during the time slot of the current frame and

ignores data during the same time slot of the next frame.

V 9 = 0, each V1/8 bit is taken into account once every 125

µs.

V10

: DIRECT MHDLC ACCESS

If V10 = 1, the Rx HDLC Controller 2 receives data issued from DIN9 input during the current

time slot (bits validated by V1/8) and DOUT7 output transmits data issued from the Tx HDLC

Controller 2.

If V10 = 0, the Rx HDLC Controller2 receives data issued from the matrix output 6 during the

current time slot; DOUT7 output delivers data issued from the matrix output 7 during the same

current time slot.

N.B: If D6 = 1, bit of General Configuration Register GCR2, the Tx HDLC controller 2 is con-

nected to matrix input 6 continuously so the HDLC frames can be sent to any DOUT

(i.e. DOUT0 to DOUT7) from the TX HDLC Controller2.

V11

: VALIDATION of CB2 pin

This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register 2).

if CSMA = 0:

V11 = 1, Contention Bus 2 pin is validated and Echo 2 pin (which is an input) is not taken into

account.

V11 = 0, Contention Bus 2 pin is high impedance during the current time slot (This pin is an

open drain output).

bit15

bit8

bit7

bit0

CH4

CH3

CH2

CH1

CH0 READ

PEN CSMA NCRC

After reset (0000)H

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels of the second 32 HDLC controller named HDLC 2

connected to input6/output6 of the switching matrix.

C1/C0 : COMMAND BITS

Command Bits

ABORT; if this command occurs during the current frame, HDLC Controller transmits seven

“1” immediately, afterwards HDLC Controller transmits “1” or flag in accordance with F bit,

generates an interrupt and waits new command such as START or CONTINUE.

If this command occurs after transmitting a frame, HDLC Controller generates an interrupt

and waits a new command such as START or CONTINUE.

START; Tx DMA Controller is now going to transfer first frame from buffer related to initial de-

scriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already transmitted.

HALT; after transmitting frame, HDLC Controller transmits “1” or flag in accordance with F bit,

generates an interrupt and is waiting new command such as START or CONTINUE.

STLC5466 Datasheet(PDF) 63 Page - STMicroelectronics

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