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STLC5466 Datasheet(PDF) 39 Page - STMicroelectronics

No. de pieza STLC5466
Descripción Electrónicos  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PDF  130 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5466 Datasheet(HTML) 39 Page - STMicroelectronics

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STLC5466
Table: switching at 16 Kb/s when ITS3=0
S1
S0
ITS3 ITS2 ITSI ITS 0 Upstream
Source: D channels of one GCI
channel
Destination: two bits of one TDM
Downstream
Source: two bits of one TDM
Destination: D channels of one
GCI channel
10
0
1
00
The contents of D channels of
GCI 0 /3 of multiplex DIN4 are
transferred into the output times-
lot of one TDM defined by the
destination register (CMAR).
D channel of GCI 0 in bit 1/2
D channel of GCI 1 in bit 3/4
D channel of GCI 2 in bit 5/6
D channel of GCI 3 in bit 7/8
The contents of the input times
lot
(same
number
as
the
number of the output timeslot)
is transferred in D channel of
GCI 0/3 of multiplex
DOUT4
bit 1/2 in D channel of GCI 0
bit 3/4 in D channel of GCI 1
bit 5/6 in D channel of GCI 2
bit 7/8 in D channel of GCI 3
01
The contents of D channels of
GCI 4/7 of multiplex DIN4 are
transferred into the output times-
lot of one TDM defined by the
destination register (CMAR).
D channel of GCI 4 in bit 1/2
D channel of GCI 5 in bit 3/4
D channel of GCI 6 in bit 5/6
D channel of GCI 7 in bit 7/8
The contents of the input times
lot
(same
number
as
the
number of the output timeslot)
is transferred in D channel of
GCI 4/7 of multiplex DOUT4.
bit 1/2 in D channel of GCI 4
bit 3/4 in D channel of GCI 5
bit 5/6 in D channel of GCI 6
bit 7/8 in D channel of GCI 7
10
The contents of D channels of
GCI 0 /3 of multiplex DIN5 are
transferred into the output times-
lot of one TDM defined by the
destination register (CMAR).
D channel of GCI 0 in bit 1/2
D channel of GCI 1 in bit 3/4
D channel of GCI 2 in bit 5/6
D channel of GCI 3 in bit 7/8
The contents of the input times
lot (same number as the
number of the output timeslot)
is transferred in D channel of
GCI 0/3 of multiplex DOUT5.
bit 1/2 in D channel of GCI 0
bit 3/4 in D channel of GCI 1
bit 5/6 in D channel of GCI 2
bit 7/8 in D channel of GCI 3
11
The contents of D channels of
GCI 4/7 of multiplex DIN5 are
transferred into the output times-
lot of one TDM defined by the
destination register (CMAR).
D channel of GCI 4 in bit 1/2
D channel of GCI 5 in bit 3/4
D channel of GCI 6 in bit 5/6
D channel of GCI 7 in bit 7/8
The contents of the input times-
lot
(same
number
as
the
number of the output timeslot)
is transferred in D channel of
GCI 4/7 of multiplex DOUT5.
bit 1/2 in D channel of GCI 4
bit 3/4 in D channel of GCI 5
bit 5/6 in D channel of GCI 6
bit 7/8 in D channel of GCI 7



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