STLC5466 datasheet(18/130 Pages) STMICROELECTRONICS

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STLC5466

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- DIN 9 or the output 6 of the matrix for the sec-

ond Time Slot Assigner.

– Its bit rate and concerned bits (4kbit/s to 64kbit/

s). 4kbit/s correspond to one bit transmitted

each two frames. This bit is repeated twice in

transmission. This bit must be present in two

consecutive frames in reception.

– Its destination for the first Time Slot Assigner:

- direct output on DOUT6

- direct output on DOUT6 and on the Contention

Bus (CB1)

- on another OTDM via input 7 of the matrix and

on the Contention Bus (CB1)

– Its destination for the second Time Slot Assign-

er:

- direct output on DOUT7

- direct output on DOUT7 and on the Contention

Bus (CB2)

- on another OTDM via input 6 of the matrix and

on the Contention Bus (CB2)

III.2.4 - Data Storage Structure

Data associated with each Rx and Tx HDLC chan-

nel is stored in external memory; The data trans-

fers between the HDLC controllers and memory

are ensured by 2*32 DMAC (Direct Memory Ac-

cess Controller) in reception and 2*32 DMAC in

transmission.

The storage structure chosen in both directions is

composed of one circular queue of buffers per

channel. In such a queue, each data buffer is

pointed to by a Descriptor located in external

memory too. The main information contained in

the Descriptor is the address of the Data Buffer, its

length and the address of the next Descriptor; so

the descriptors can be linked together.

This structure allows to:

– Store receive frames of variable and unknown

length

– Read transmit frames stored in external memory

by the host

– Easily perform the frame relay function.

III.2.4.1 - Reception

At the initialization of the application, the host has

to prepare two Initialization Block registers. Each

Initialization Block located in shared memory con-

tains the first receive buffer descriptor address for

each channel, and the receive circular queues. At

the opening of a receive channel, the DMA con-

troller reads the address of the first buffer descrip-

tor

corresponding

this

channel

the

initialization Block. Then, the data transfer can oc-

cur without intervention of the processor.

A new HDLC frame always begins in a new buffer.

A long frame can be split between several buffers

if the buffer size is not sufficient. All the information

concerning the frame and its location in the circu-

lar queue is included in the Receive Buffer De-

scriptor:

– The Receive Buffer Address (RBA),

– The size of the receive buffer (SOB),

– The number of bytes written into the buffer

(NBR),

– The Next Receive Descriptor Address (NRDA),

– The status concerning the receive frame,

– The control of the queue.

III.2.4.2 - Transmission

In transmission, the data is managed by a similar

structure as in reception

By the same way, a frame can be split up between

consecutive transmit buffers.

The main information contained in the Transmit

Descriptor are:

– transmit buffer address (TBA),

– number of bytes to transmit (NBT) concerning

the buffer,

– next transmit descriptor address (NTDA),

– status of the frame after transmission,

– control bit of the queue,

– CSMA/CR priority (8 or 10).

III.2.4.3 - Frame Relay

The principle of the frame relay is to transmit a

frame which has been received without treatment.

A new heading is just added. This will be easily

achieved, taking into account that the queue struc-

ture allows the transmission of a frame split be-

tween several buffers.

III.2.5 - Transparent Modes

In the transparent mode, the

Multi-HDLC transmits

data in a completely transparent manner without

performing any bit manipulation or Flag insertion.

The transparent mode is per byte function; the

channel used for this mode is n*64kb/s mandato-

ry.

Two transparent modes are offered:

– First mode: for the receive channels, the Multi-

HDLC continuously writes received bytes (from

the received timeslot) into the external memory

as specified in the current receive descriptor

without taking into account the Fill Character

– Second mode: the Fill Character Register spec-

ifies the “fill character” which must be taken into

account. In reception, the “fill character” is de-

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