STLC5466 datasheet(38/130 Pages) STMICROELECTRONICS

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STLC5466

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CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multi-

plex OTDMq:

: SEQUENCE INTEGRITY

SI = 1, the delay is always: (31 - ITSx) + 32 + OTSy (constant delay).

SI = 0, the delay is minimum to pass through the data memory (variable delay).

LOOP: LOOPBACK per channel relevant if two connections has been established (bidirectional or not).

LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq.

OTSV = 1, transparent Mode LOOPBACK.

OTSV = 0, not Transparent Mode LOOPBACK.

OTSV : OUTPUT TIME SLOT VALIDATED

OTSV = 1, OTSy OTDMq is enabled.

OTSV = 0, OTSy OTDMq is High impedance.

(OTSy: Output Time slot with 0

≤ y ≤ 31; OTDMq: Output Time Division Multiplex with 0 ≤ q ≤ 7).

S1/S0 : Source

Source for each timeslot of DOUT0/7

Data Memory (Normal case)

Connection Memory

D channels from/to GCI multiplexes (See note and table hereafter)

Pseudo Random Sequence Generator delivers sequences.

Hyperchannel at n x 64 Kb/s is possible.

Note:

• Connection

When the source of D channels is selected (GCI channels defined by ITS 1/0) and when the

destination is selected (Output timeslot defined by OTS 0/4; output TDM defined by OM 0/2) the

upstream connection is set up; the downstream connection (reverse direction TDM to GCI) is

set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR must be written at”0”.

•Release

Remember: write S1=1, S0=0 and ITS 2 bit = 0 to release the downstream connection; the up-

stream connection is released when the source changes.

STLC5466 Datasheet(PDF) 38 Page - STMicroelectronics