STLC5466 datasheet(15/130 Pages) STMICROELECTRONICS

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STLC5466

III.1.4 - Loop Back Function

Any time slot of an Output TDM can be internally

looped back on the time slot which has the same

TDM number and the same TS number

(OTDMi, TSj) ----> (ITDMi, TSj).

In the case of a bidirectional connection, only the

one specified by the microprocessor is concerned

by the loop back (see Figure).

III.1.5 - Delay through the Matrix

III.1.5.1 - Variable Delay Mode

In the variable delay mode, the delay through the

matrix depends on the relative positions of the in-

put and output time slots in the frame.

So, some limits are fixed:

– the maximum delay is a frame + 2 time slots,

– the minimum delay is programmable.

Three time slots if IMTD = 1, in this case n = 2 in

the formula hereafter or

two time slots if IMTD = 0, in this case n = 1 in

the same formula (see Paragraph “Switching

Matrix Configuration Register SMCR (0C)H”).

All the possibilities can be ranked in three cases:

a) If OTSy > ITSx + n then the variable delay is:

OTSy - ITSx Time slots

b) If ITSx < OTSy < ITSx+n then the variable delay

is:

OTSy - ITSx + 32 Time slots

c) OTSy < ITSx then the variable delay is:

32 - (ITSx - OTSy) Time slots.

N.B. Rule b) and rule c) are identical.

For n = 1 and n = 2, (see Figure).

III.1.5.2 - Sequence Integrity Mode

In the sequence integrity mode (SI = 1, bit located

in the Connection Memory), the input time slots

are put out 2 frames later (see Figure). In this

case, the delay is defined by a single expression:

Constant Delay = (32 - ITSx) + 32 + OTSy

So, the delay in sequence integrity mode varies

from 33 to 95 time slots.

III.1.6 - Connection Memory

III.1.6.1 - Description

The connection memory is composed of 256 loca-

tions addressed by the number of OTDM and TS

(8x32).

Each location permits:

– to connect each input time slot to one output

time slot (If two or more output time slots are

connected to the same input time slot number,

there is broadcasting).

– to select the variable delay mode or the se-

quence integrity mode for any time slot.

– to loop back an output time slot. In this case the

contents of an input time slot (ITSx, ITDMp) is

the same as the output time slot (OTSx, OT-

DMp).

– to output the contents of the corresponding con-

nection memory instead of the data which has

been stored in data memory.

– to output the sequence of the pseudo random

sequence generator on an output time slot: a

pseudo random sequence can be inserted in

one or several time slots (hyperchannel) of the

same Output TDM; this insertion must be ena-

bled by the microprocessor in the configuration

– to define the source of a sequence by the pseu-

do random sequence analyser: a pseudo ran-

dom sequence can be extracted from one or

several time slots (hyperchannel) of the same

Input TDM and routed to the analyser; this ex-

traction can be enabled by the microprocessor

in the configuration register of the matrix (SM-

CR).

– to assert a high impedance level on an output

time slot (disconnection).

– to deliver a programmable 256-bit sequence

during 125 microseconds on the Programmable

synchronization Signal pin (PSS).

III.1.6.2 - Access to Connection Memory

Supposing that the Switching Matrix Configuration

microprocessor, it is possible to access to the con-

nection memory from microprocessor with the

help of two registers:

– Connection Memory Data Register (CMDR) and

– Connection Memory Address Register (CMAR).

III.1.6.3 - Access to Data Memory

To extract the contents of the data memory it is

possible to read the data memory from microproc-

essor with the help of the two registers:

– Connection Memory Data Register (CMDR) and

– Connection Memory Address Register (CMAR).

III.1.7 - Switching at 32 Kbit/s

Four TDMs can be programmed individually to

carry 64 channels at 32 Kbit/s (only if these TDMs

are at 2 Mbit/s).

Two bits (SW0/1) located in SMCR define the type

of channels of two couples of TDMs.

SW0 defines TDM0 and TDM4 (GCI0) and SW1

defines TDM1 and TDM5 (GCI1).

If TDM0 or/and TDM1 carry 64 channels at 32

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