STLC5466 datasheet(35/130 Pages) STMICROELECTRONICS

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STLC5466

N.B. If DOUT4 and DOUT5 are GCI Multiplexes: then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.

VI.7 - Switching Matrix Configuration Register

SMCR (0C)H

DEL(i); : DELAYED Multiplex(i) with (0

≤ i ≤ 7).

When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.

If TDM is at 2048 kb/s,1/2 bit-time is 244 ns

If TDM is at 4096 kb/s,1/2 bit-time is 122 ns

OMV (i) : Output Multiplex Validated 0/7

OMVi =1, condition to have DOUT(i) pin active (0

≤ i ≤ 7).

OMVi =0, DOUT(i) pin is High impedance continuously (0

≤ i ≤ 7).

bit15

bit8

bit7

bit0

SW1

SW0

DR64 DR44 DR24 DR04 AISD

SGC

SAV

SGV

TS1

TS0

IMTD

After reset (0000)H

IMTD

: Increased Minimum Throughput Delay

When SI = 0 (bit of CMDR, variable delay mode):

IMTD = 1, the minimum delay through the matrix memory is three time slots whatever the se-

lected TDM output.

IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the select-

ed TDM output. In this case the input TDM’s cannot be delayed versus the Frame Synchroni-

zation (use of IMCR is limited) and the output TDM’s cannot be advanced versus the Frame

Synchronization (use of OMCR is limited).

TS0

: Tristate 0

TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate: “0” is at low impedance, “1” is at low

impedance and the third state is high impedance.

TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain: “0” is at low impedance, “1” is at high

impedance.

TS1

: Tristate 1

TS1 = 1, the DOUT4/5 pins are tristate: “0” is at low impedance, “1” is at low impedance and

the third state is high impedance.

TS1 = 0, the DOUT4/5 pins are open drain: “0” is at low impedance, “1” is at high impedance.

SGV

: Pseudo Random Sequence Generator Validated

SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the

related time slot(s).

SGV = 0, PRS Generator is reset.”0” are transmitted during the related time slot.

DEL (i)

ST (i) 1

ST (i) 0

STEP for each Output Multiplex 0/7 delayed or not

Each bit is transmitted on the rising edge of the double clock without

delay. Bit0 is defined by Frame synchronization Signal.

Each bit is transmitted with 1/2 bit-time delay.

Each bit is transmitted with 1 bit-time delay.

Each bit is transmitted with 2 bit-time delay

Each bit is transmitted with 1/2 bit-time advance.

Each bit is transmitted with 1 bit-time advance.

Each bit is transmitted with 2 bit-time advance

STLC5466 Datasheet(PDF) 35 Page - STMicroelectronics

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