STLC5466 datasheet(32/130 Pages) STMICROELECTRONICS

32 / 130 page

STLC5466

32/130

TSV

: Time Stamping Validated

TSV = 1, the time stamping counter becomes a free binary counter and counts down from

65535 to 0 in step of 250 microseconds (Total = 16384ms). So if an event occurs when the

counter indicates A and if the next event occurs when the counter indicates B then:

t = (A-B) x 250 microseconds is the time which has passed between the two events which have

been stored in memory by the Interrupt Controller (for Rx C/I and Rx MON CHANNEL only).

TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter

constitute a Watch Dog or a Timer.

EVM

: EXTERNAL VCXO MODE

EVM=1,VCXO Synchronization Counter is divided by 32.

EVM=0,VCXO Synchronization Counter is divided by 30.

: First HDLC controller connected to MATRIX

D7 = 1, the first transmit HDLC controller is connected to matrix input 7, the DIN7 signal is ig-

nored.

D7 = 0, the DIN7 signal is taken into account by the matrix, the first transmit HDLC controller is

ignored by the matrix.

SYN0/1 : SYNCHRONIZATION

SYN0/1: these two bits define the signal applied on FRAMEA/B inputs.

HCL

: HIGH BIT CLOCK

This bit defines the signal applied on CLOCKA/B inputs.

HCL = 1, bit clock signal is at 8192kHz (or 6144kHz)

HCL= 0, bit clock signal is at 4096kHz (or 3072kHz)

CSD

: Clock Supervision Deactivation

CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked.

CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this

disappearance.

SELB

: SELECT B

SELB = 1, FRAME B and CLOCK B must be selected.

SELB = 0, FRAME A and CLOCK A must be selected.

BSEL

: B SELECTED (this bit is read only)

BSEL = 1, FRAME B and CLOCK B are selected.

BSEL = 0, FRAME A and CLOCK A are selected.

SCL

: Single Clock

This bit defines the signal delivered by DCLK output pin.

CLOCKA/B inputs at 4096kHz or 8192kHz

SCL = 1, Data Clock is at 2048kHz.

SCL = 0, Data Clock is at 4096kHz.

CLOCKA/B inputs at 3072kHz or 6144kHz

SCL = 1, Data Clock is at 1536kHz.

SCL = 0, Data Clock is at 3072kHz.

SYN1

SYN0

Signal applied on FRAMEA/B inputs

SY Interface

GCI Interface (the signal defines the first bit of the frame)

Vstar Interface (the signal defines third bit of the frame)

Not used

STLC5466 Datasheet(PDF) 32 Page - STMicroelectronics

STLC5466 Datasheet(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL