STLC5466 datasheet(19/130 Pages) STMICROELECTRONICS

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STLC5466

tected in each timeslot and will not be trans-

ferred to the external memory. The detection of

“Fill character” marks the end of a message and

generates an interrupt if BINT=1). When the “Fill

character” is not detected a new message is re-

ceiving.

As for the HDLC mode the correspondence be-

tween the physical time slot and the logical chan-

nel is fully defined in the two Time Slot Assigners

(Time slot used or not used, logical channel

number, source, destination).

III.2.6 - Command of the HDLC Channels

The microprocessor is able to control each HDLC

receive and transmit channel. Some of the com-

mands are specific to the transmission or the re-

ception but others are identical.

III.2.6.1 - Reception Control

– The configuration of the controller operating

mode is: HDLC mode or Transparent mode.

– The control of the controller: START, HALT,

CONTINUE, ABORT.

START: On a start command, the RxDMA con-

troller reads the address of the first descriptor in

the initialization block memory and is ready to

receive a frame.

HALT: For overloading reasons, the microproc-

essor can decide to halt the reception. The DMA

controller finishes transfer of the current frame

to external memory and stops. The channel can

be restarted on CONTINUE command.

CONTINUE: The reception restarts in the next

descriptor.

ABORT: On an abort command, the reception is

instantaneously stopped. The channel can be

restarted on a START or CONTINUE command.

– Reception

FLAG

(01111110)

IDLE

(11111111) between Frames.

– Address recognition. The microprocessor de-

fines the addresses that the Rx controller has to

take into account.

– In transparent mode: “fill character” register is

selected or not.

III.2.6.2 - Transmission Control

– The configuration of the controller operating

mode is: HDLC mode or Transparent mode.

– The control of the controller: START, HALT,

CONTINUE, ABORT.

START: On a start command, the Tx DMA con-

troller reads the address of the first descriptor in

the initialization block memory and tries to trans-

mit the first frame if End Of Queue is not at “1”.

HALT: The transmitter finishes to send the cur-

rent frame and stops.The channel can be re-

started on a CONTINUE command.

CONTINUE: if the CONTINUE command occurs

after HALT command, the HDLC Transmitter re-

starts by transmitting the next buffer associated

to the next descriptor.

If the CONTINUE command occurs after an

ABORT command which has occurred during a

frame, the HDLC transmitter restarts by trans-

mitting the frame which has been effectively

aborted by the microprocessor.

ABORT: On an abort command, the transmis-

sion of the current frame is instantaneously

stopped, an ABORT sequence “1111111” is

sent, followed by IDLE or FLAG bytes. The

channel can be restarted on a START or CON-

TINUE command.

– Transmission of FLAG (01111110) or IDLE

(111111111) between frames can be selected.

– CRC can be generated or not. If the CRC is not

generated by the HDLC Controller, it must be lo-

cated in the shared memory.

– In transparent mode: “fill character” register can

be selected or not.

III.3 - C/I and Monitor

III.3.1 - Function Description

The

Multi-HDLC is able to operate both GCI and

V* links. The TDM DIN/DOUT 4 and 5 are internal-

ly connected to the CI and Monitor receivers/trans-

mitters. Since the controllers handle up to 16CI

and 16 Monitor channels simultaneously, the Mul-

ti-HDLC can manage up to 16 level 1 circuits.

The Multi-HDLC can be used to support the CI and

monitor channels based on the following proto-

cols:

– ISDN V* protocol

– ISDN GCI protocol

– Analog GCI protocol.

III.3.2 - GCI and V* Protocol

A TDM can carry 8 GCI channels or V* channels.

The monitor and S/C bytes always stand at the

same position in the TDM in both cases.

CGI Channel 0

CGI Channel 1 to Channel 6

CGI Channel 7

TS0

TS1

TS2

TS3

TS28

TS29

TS30

TS31

MON

S/C

MON

S/C

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