STLC5466 datasheet(75/130 Pages) STMICROELECTRONICS

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STLC5466

VII.4 - Receive & Transmit HDLC Frame Interrupt

This word is located in the HDLC interrupt queue; IQSR Register indicates the size of this HDLC interrupt

queue located in the external memory.

Transmitter

Receiver

bit15

bit8

bit7

bit 0

CFT/CFR

BE/BF

HALT

EOQ

RRLF/ERF

: New Status.

Before writing the features of event in the external memory the Interrupt Controller reads the NS

bit:

if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame

which has been transmitted or received.

if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).

When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new

status. This location becomes free for the Interrupt Controller.

: 32 HDLC controller

A5 = 1, Second 32 HDLC controller (connected to Dout6/ Din6 of the switching matrix).

A5 = 0, First 32 HDLC controller (connected to Dout7/ Din7 of the switching matrix).

: Tx = 1, Transmitter

A4/0

: Tx HDLC Channel 0 to 31

RRLF : Ready to Repeat Last Frame

In consequence of event such as Abort Command HDLC, Controller is waiting Start or Continue

EOQ

: End of Queue

The Transmit DMA Controller has encountered the current Transmit Descriptor with EOQ at “1”.

DMA Controller is waiting “Continue” from microprocessor.

HALT : The Transmit DMA Controller has received HALT from the microprocessor; it is waiting “Contin-

ue” from microprocessor.

: Buffer empty

If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMA Controller puts BE at “1” when the

buffer has been emptied.

CFT

: Correctly Frame Transmitted

A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is

at ‘1’. CFT is located in the last descriptor if several descriptors are used to define a frame.

: Tx = 0, Receiver

A4/0

: Rx HDLC Channel 0 to 31

ERF

: Error detected on Received Frame

An error such as CRC not correct, Abort, Overflow has been detected.

EOQ

: End of Queue

The Receive DMA Controller has encountered the current receive Descriptor with EOQ at “1”.

DMA Controller is waiting “Continue” from microprocessor.

HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the

microprocessor; it is waiting “Continue” or “Start” from the microprocessor.

: Buffer Filled

If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has

filled the current buffer with data from the received frame.

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