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STLC5466 Datasheet(PDF) 9 Page - STMicroelectronics |
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STLC5466 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 130 page ![]() 9/130 STLC5466 41 NDIS/NCS2 I3_ft If 386EX interface is not selected: DOUT 0/7 Not Disable. When this pin is at 0V, the Data Output 0/7 are at high impedance. Wired at VDD if not used. If 386EX interface is selected: NCS2 (Chip Select 2) equivalent to NCS1. Chip Select 2: external memory is selected During Chip select (NCS2=0), the output Ready (pin 59) is low impedance and outside Chip select (NCS2=1), the output Ready is high impedance. 7 CB1 O6D_ft Contention Bus (CSMA/CR) for 1st 32 HDLC Controller 8 EC1 I3_ft Echo for 1st 32 HDLC Controller. Wired at VSS if not used. 128 CB2 O6D_ft Contention Bus (CSMA/CR) for 2nd 32 HDLC Controller 130 EC2 I3_ft Echo for 2nd 32 HDLC Controller. Wired at VSS if not used. BOUDARY SCAN 42 NTRST I4_ft Reset for boundary scan 47 TMS I2_ft Mode Selection for boundary scan 48 TDI I2_ft Input Data for boundary scan 49 TDO O3T_ft Output Data for boundary scan 50 TCK I4_ft Clock for boundary scan MICROPROCESSOR INTERFACE 64 MOD0 I1_ft 1 1 0 0 1 1 0 0 65 MOD1 I1_ft 1 1 0 0 0 0 1 1 66 MOD2 I1_ft 0 1 1 0 01 10 80C188 80C186 68000 68020 ST9 ST10 m ST10Nm 386EX 3 NRESET I3_ft Circuit Reset 53 NCS0 I3_ft Chip Select 0: internal registers are selected 54 NCS1 I3_ft Chip Select 1: external memory is selected During Chip select (NCS1=0), the output Ready (pin 59) is low impedance and outside Chip select (NCS1=1), the output Ready is high impedance. 55 INT0 O3_ft Interrupt generated by HDLC, RxC/I or RxMON. Active high. 56 INT1 O3_ft Interrupt1.This pin goes to 5V when the selected clock A (or B) has disap- peared; 250 µs after reset this pin goes to 5V also if clock A is not present. 6 WDO O3_ft Watch Dog Output.This pin goes to 5V during 250 µs when the microprocessor has not reset the Watch Dog during the programmable time. 57 SIZE0/NLDS/NLBA I3_ft Transfer Size0 (68020)/Lower Data Stobe/Local Bus Access# when 386EX 58 SIZE1/NBHE/NUDS I3_ft Transfer Size1(68020)/Bus High Enable (Intel) / Upper Data Strobe (68000) 59 NDSACK0/ NDTACK/ NREADY O6T_ft/ O6T_ft/ O6D_ft Data Strobe, Acknowledge and Size0 (68020)/ Data Transfer Acknowledge (68000 and ST10)/ READY# (386EX) 60 NDSACK1/ READY O6T_ft O6T_ft Data Strobe, Acknowledge and Size1 (68020)/ Data Transfer Acknowledge (Intel) 61 NAS/ ALE/NADS I3_ft Address Strobe(Motorola) / Address Latch Enable(Intel) / Address Status 386EX 62 R/W / NWR I3_ft Read/Write (Motorola) / Write(Intel) Pin N° Symbol Type Function Type ft: five volts tolerant fnt: five volts not tolerant TTL I1_ft = Input TTL I2_ft = I1_ft+pull up I3_ft = I1_ft+hysteresis I4_ft = I3_ft+pull up TTL I/O6 _ft = Input TTL/ Output TTL 6 mA I5_ft = I3_ft+pull down; TTL O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate O6_ft = Output TTL 6mA TTL O6D_ft = Output TTL 6mA, Open Drain O6DT_ft = Output TTL 6mA, Open Drain or Tristate CMOS I/O8_fnt = Input TTL, /Output CMOS 8mA; O8T_fnt = Output CMOS 8mA I/O8_fnt = Input TTL, /Output CMOS 8mA CMOS O4_fnt = Output CMOS 4mA |
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