STLC5466 datasheet(47/130 Pages) STMICROELECTRONICS

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STLC5466

C1/C0 : STATUS BITS

P0/1

: PROTOCOL BITS

F: Flag

F = 1; flags are transmitted between closing flag of current frame and opening flag of next frame.

F = 0; “1” are transmitted between closing flag of current frame and opening flag of next frame.

NCRC : CRC NOT TRANSMITTED

NCRC = 1, the CRC is not transmitted at the end of the frame.

NCRC = 0, the CRC is transmitted at the end of the frame.

CSMA : Carrier Sense Multiple Access with Contention Resolution

CSMA = 1, CB1 output and the Echo Bit are taken into account during this channel transmission

by the TxHDLC.

CSMA = 0, CB output and the Echo Bit are defined by V11, bit of Time slot Assigner Data Reg-

ister TADR1 (16)H.

PEN

: CSMA PENALTY significant if CSMA = 1

PEN = 1, the penalty value is 1; a transmitter which has transmitted a frame correctly will count

(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the buffer descriptor related to the frame.

PEN = 0, the penalty value is 2; a transmitter which has transmitted a frame correctly will count

(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the transmit descriptor related to the frame).

: Common flag

CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next

frame is ready to be transmitted.

CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.

STATUS BITS read by the microprocessor

ABORT; the microprocessor has written ABORT or the transmitted frame has been aborted

by the HDLC Controller and it waits new command such as START or CONTINUE.

START; the microprocessor has written START.The HDLC Controller has not taken into ac-

count the command yet.

CONTINUE; the HDLC Controller has taken into account the command START.

TX DMA Controller is transferring frames.

CONTINUE; Tx DMA Controller is now going to transfer next frame from buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already transmitted.

Transmission Mode

HDLC

Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken

into account.

Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not

taken into account.

Reserved

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