STLC5466 datasheet(23/130 Pages) STMICROELECTRONICS

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STLC5466

III.6.2.2 - Read Fetch Memory

When the microprocessor delivers the address

word named An to read data named [An] out of the

shared memory in fact it reads data [An] from the

Read Fetch Memory (64 words).

The number of wait cycle for the microprocessor is

strongly reduced. If An, address word delivered by

the microprocessor, and data [An] are already in

the Read Fetch Memory and validated then there

is no wait time for the microprocessor.

The source of [An] is truly the shared memory

whatever An.

Data [An] if validated in Fetch Memory and Data

[An] in shared memory are always the same.

III.6.2.3 - Definition of the Interface for the dif-

ferent microprocessors

The signals connected to the microprocessor in-

terface are presented on the following figures for

the different microprocessor (see Figures).

III.7 - Memory Interface

III.7.1 - Function Description

The memory interface allows the connection of

Synchronous Dynamic RAM. The memory inter-

face will address up to 16 Megabytes. The memo-

ry location is always organized in 16 bits.

The memory is shared between the Multi-HDLC

and the microprocessor. The access to the mem-

ory is arbitrated by an internal function of the cir-

cuit: the bus arbitration.

III.7.2 - Choice of memory versus microproces-

sor and capacity required

The memory interface depends on the memory

chips which are connected. The memory chips will

be chosen versus their organization.

Example1: if the application requires 8 or 16 bit

µProcessor and 1 Megaword Shared memory

size, one capability is offered:

– 1 SDRAM Circuit (1Mx16).

Example2: if the application requires 16 bit

µProc-

essor and 4 Megaword Shared memory size,

three capabilities are offered:

– 4 SDRAM Circuits (1Mx16) or

– 4 SDRAM Circuits (4Mx4) or

– 1 SDRAM Circuit (4Mx16).

.Example3: if the application requires 8 Megaword

Shared memory size three capabilities are offered:

– 8 SDRAM Circuits (4Mx4) or

– 2 SDRAM Circuits (4Mx16) or

– 2 SDRAM Circuit (8Mx8).

III.7.3 - Memory Cycle

Some parameters are frozen:

– Burst Read and Single Write.

– The Burst Length is 4.

– The burst data is addressed in sequential mode.

The programmable parameters are:

– Latency Mode

– selected circuit organisation

– the

exchanges

between

Multi-HDLC

and

SDRAM are at the Master Clock frequency

(33MHz, 50MHz, 66MHz)

III.7.4 - Memories composed of different cir-

cuits

III.7.4.1 - Memory obtained with 1M x16 SDRAM

circuit

The Address bits delivered by the Multi-HDLC for

1M x 16 SDRAM circuits are:

– ADM11 for Bank select corresponding with A20

delivered by the microprocessor

– ADM0/10 for Row address inputs corresponding

with A9/19 delivered by the microprocessor

– ADM0/7 for Column address inputs correspond-

ing with A1/8 delivered by the microprocessor

III.7.4.2 - Memory obtained with 2M x 8 SDRAM

circuit

The Address bits delivered by the Multi-HDLC for

2M x 8 SDRAM circuits are:

– ADM11 for Bank select corresponding with A21

delivered by the microprocessor

– ADM0/10 for Row address inputs corresponding

with A10/20 delivered by the microprocessor

– ADM0/8 for Column address inputs correspond-

ing with A1/9 delivered by the microprocessor

Signals

A22

A21

Signals

or equiva-

lent

NCE3

NCE2

NCE1

UDQM

NCE0

LDQM

Signals

A0 or equivalent

NLDS

NUDS

UDQM

LDQM

STLC5466 Datasheet(PDF) 23 Page - STMicroelectronics

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