STLC5466 datasheet(33/130 Pages) STMICROELECTRONICS

33 / 130 page

33/130

STLC5466

VI.3 - Input Multiplex Configuration Register 0

IMCR0 (04)H

See definition in next Paragraph.

AFAB

: Advanced Frame A/B Signal

AFAB = 1, the advance of FRAMEA Signal and FRAMEB Signal is 0.5 bit time versus the signal

FRAMEA (or B).

AFAB = 0, FRAMEA Signal and FRAMEB Signal are in accordance with the clock timing.

MBL

: Memory Bus Low impedance

MBL = 1, the shared memory bus is at low impedance between two memory cycles and also at

low impedance during a memory cycle.

The memory bus includes Control bus, Address bus except Data bus. One Multi-HDLC can be

connected to the shared memory. 16 pull-up resistors must be connected on the data bus.

MBL = 0, the shared memory bus is at high impedance between two memory cycles and at

low impedance during a write memory cycle.

Several Multi-HDLCs can be connected to the shared memory. One pull-up resistor is recom-

mended on each wire (Control bus, Address bus, Data bus).

SBV

: Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and down-

stream).

SBV=1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel

can be received from any input timeslot; when this word is received identical twice consecutive-

ly, it is stored in the external shared memory and an interrupt is generated if not masked (like

the reception of primitive from C/I channel).

Sixteen independent detections are performed if the contents of any input timeslot is switched

in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0

≤ n

≤ 7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes.

In transmission a six bit word (A, E, S1/S4) can be transmitted continuously to any output times-

lot via the TCIR. This word (A, E, S1/S4) is set instead of primitive (C1, C2, C3, C4) and A, E

bits received from the timeslot 4n+3 of two GCI multiplexes and the new contents of this timeslot

4n+3 must be switched on the selected output timeslot.

SBV=0, the 16 six bit detections are not validated.

bit15

bit8

bit7

bit0

LP3

DEL3 ST(3)1 ST(3)0 LP2

DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0

After reset (0000)H

During the whole of cycle duration

On the outside of cycle

MBL

Bus

Write cycle

Read cycle

A, C

STLC5466 Datasheet(PDF) 33 Page - STMicroelectronics

STLC5466 Datasheet(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL