STLC5466 datasheet(60/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.33 - General Configuration Register 2

GCR2 (42)H

bit15

bit8

bit7

bit0

SWAP

BYP

NINIT

MC1

MC0

After reset (0000)H id 512ms

MC0/1 :

Master Clock0/1

MC0/1: these two bits take into account the signal applied on MCLK pin. So whatever the fre-

quency may be, the internal circuit operates with the appropriate internal clock and the exchang-

es between Multi-HDLC and SDRAM are at the Master Clock frequency.

The duration of the pulse named token ring is equal to the period of master clock applied

to MCLK pin.

NINIT : NOT INIT

NINIT=1; when the microprocessor writes the SDRAM register with NINIT=1, the SDRAM will

not be initialized.

NINIT=0; when the microprocessor writes the SDRAMR register with NINIT=0, the SDRAM will

be initialized in accordance with LT0/2 bits (of SDRAMR).

In case of several Multi-HDLC’s connected to the same memory, only one of them initializes and

refreshes the SDRAM.

So the GCR2 registers of these Multi-HDLC’s are same contents except this bit which initializes

the SDRAM.

BYP

: BYPASS

BYPASS=1; the write FIFO and the read fetch memory located in the microprocessor interface

are bypassed.

BYPASS=0; the write FIFO and the read fetch memory located in the microprocessor interface

are used when the microprocessor accesses the shared memory.

: HDLC2 connected to MATRIX

D6=1, the transmit HDLC2 is connected to matrix input 6, the DIN6 signal is ignored.

MC1

MC0

Signal applied on MCLK pin

Exchanges between Multi-HDLC and

SDRAM with common clock at

66MHz

50MHz

33MHz

Not used

STLC5466 Datasheet(PDF) 60 Page - STMicroelectronics

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