ADRF6620ACPZ-R7 datasheet(27/52 Pages) AD

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Data Sheet

ADRF6620

Rev. 0 | Page 27 of 52

The following equations can be used to determine the N value and

PLL frequency:

VCO

PFD

MOD

FRAC

INT

LO_DIVIDER

PFD

where:

fPFD is the phase frequency detector frequency.

fVCO is the voltage controlled oscillator frequency.

N is the fractional divide ratio (INT + FRAC/MOD)

INT is the integer divide ratio programmed in Register 0x02.

FRAC is the fractional divider programmed in Register 0x03.

MOD is the modulus divide ratio programmed in Register 0x04.

fLO is the LO frequency going to the mixer core when the loop is

locked.

LO_DIVIDER is the final divider block that divides the VCO

frequency down by 1, 2, 4, or 8 before it reaches the mixer

(see Table 12). This control is located in the LO_DIV_A bits

(Register 0x22, Bits[4:3]).

Table 12. LO Divider

LO_DIV_A (Register 0x22, Bits[4:3])

LO_DIVIDER

The lock detect signal is available as one of the selectable outputs

through the MUXOUT pin; a logic high indicates that the loop

is locked. The MUXOUT pin is controlled by the REF_MUX_SEL

bits (Register 0x21, Bits[6:4]); the PLL lock detect signal is the

default configuration.

To ensure that the PLL locks to the desired frequency, follow the

proper write sequence of the PLL registers. The PLL registers must

be configured accordingly to achieve the desired frequency, and the

last writes must be to Register 0x02 (INT_DIV), Register 0x03

(FRAC_DIV), or Register 0x04 (MOD_DIV). When one of these

registers is programmed, an internal VCO calibration is initiated,

which is the last step in locking the PLL.

The time it takes to lock the PLL after the last register is written

can be broken down into two parts: VCO band calibration and

loop settling.

After the last register is written, the PLL automatically performs

a VCO band calibration to choose the correct VCO band. This

calibration takes approximately 5120 PFD cycles. For a 40 MHz

fPFD, this corresponds to 128 µs. After calibration is complete, the

feedback action of the PLL causes the VCO to eventually lock to

the correct frequency. The speed with which this locking occurs

depends on the nonlinear cycle-slipping behavior, as well as the

small-signal settling of the loop. For an accurate estimation of

the lock time, download the ADIsimPLL tool, which correctly

captures these effects. In general, higher bandwidth loops tend

to lock more quickly than lower bandwidth loops.

Additional LO Controls

To access the LO signal going to the mixer core through the

LOOUT+ and LOOUT− pins (Pin 21 and Pin 22), enable the

LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct

monitoring of the LO signal to the mixer for debug purposes; or the

LO signal can be used to daisy-chain many devices synchronously.

One ADRF6620 can serve as the master where the LO signal is

sourced, and the subsequent slave devices share the same LO signal

from the master. This flexibility substantially eases the LO require-

ments of a system with multiple LOs.

The LO output drive level is controlled by the LO_DRV_LVL

bits (Register 0x22, Bits[8:7]). Table 13 shows the available drive

levels.

Table 13. LO Drive Level

LO_DRV_LVL (Register 0x22, Bits[8:7])

Amplitude (dBm)

−4

0.5

4.5

SERIAL PORT INTERFACE (SPI)

The SPI port of the ADRF6620 allows the user to configure the

device through a structured register space provided inside the

chip. Registers are accessed via the serial port interface and can

be written to or read from via the serial port interface.

The serial port interface consists of three control lines: SCLK,

SDIO, and CS. SCLK (serial clock) is the serial shift clock. The

SCLK signal clocks data on its rising edge. SDIO (serial data

input/output) is an input or output depending on the instruction

being sent and the relative position in the timing frame. CS

(chip select bar) is an active low control that gates the read and

write cycles. The falling edge of CS, in conjunction with the rising

edge of SCLK, determines the start of the frame. All SCLK and

SDIO activity is ignored when CS is high. Table 6 and Figure 2

show the serial timing and its definitions.

The ADRF6620 protocol consists of seven register address bits,

followed by a read/write indicator and 16 data bits. Both the

address and data fields are organized from MSB to LSB.

On a write cycle, up to 16 bits of serial write data are shifted in,

MSB to LSB. If the rising edge of CS occurs before the LSB of

the serial data is latched, only the bits that were clocked in are

written to the device. If more than 16 data bits are shifted in,

the 16 most recent bits are written to the device. The ADRF6620

input logic level for the write cycle supports a logic level as low

as 1.8 V.

On a read cycle, up to 16 bits of serial read data are shifted out,

MSB to LSB. Data shifted out beyond 16 bits is undefined. It is

not necessary for readback content at a given register address to

correspond with the write data of the same address. The output

logic level for a read cycle is 2.5 V.

ADRF6620ACPZ-R7 Datasheet(PDF) 27 Page - Analog Devices

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